Network based machine instruction generator for design verificat

Details Network based machine instruction generator for design verificat Network based machine instruction generator for design verificat

1994-09-14

1995-10-03

Beausoliel, Jr., Robert W.

Boots, shoes, and leggings

371 27, 39518313, G06F 1100, G01R 3128

Patent

active

054559383

ABSTRACT:
A machine instruction generator which generates a sequence of processor test instructions by traversing sites on a network, each of which has a local state corresponding to a group of related machine instructions. The sequence of processor instructions are generated by selecting a site on the network, randomly selecting a machine instruction available at that site by virtue of the local state, adding that machine instruction to a diagnostic file, and moving to an adjacent site. The sequence of machine instructions is concurrently tested on a functional model of the processor and a logical design of the processor. Any discrepancy in the results of these two tests indicates that a bug has been found in the processor. Network paths leading to the discovery of processor bugs may be represented in new generation networks produced by reinforcement learning or genetic operations.

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