Nested chopper delta-sigma modulator

Details Nested chopper delta-sigma modulator Nested chopper delta-sigma modulator

2002-11-19

2003-10-28

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S118000, C341S172000

Reexamination Certificate

active

06639532

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to circuitry and, more particularly, to chopper circuitry for reducing residual noise caused by a mismatch between input chopper switches.
2. Description of the Related Art
In the application of analog to digital (ADC) converters, the accuracy and feasibility of a delta-sigma modulator (DSM) make it popular for implementation in many circuits, such as audio codec circuits, communication circuits, sensor circuits, and instrumentation circuits. Nevertheless, the performance of the delta-sigma modulator (DSM) is sensitive to input noise, which is caused by switches, operational amplifiers (op amps), and digital circuits, and such noise will degrade the dynamic range of the input signal.
In the low frequency band, the increase in flicker noise is proportional to the decrease in frequency. In the relative-low frequency band, the offset will dominate the noise. Especially in sensor interface circuits, system performance is limited. In the prior art, correlated double sampling, self-calibrating operational amplifiers (op amps), and chopper-stabilized techniques are used to deal with this type of noise. These techniques are generally grouped in two categories one of which is referred to as autozeroing and the other is referred to as chopping. These approaches can also be applied to an amplifier and integrator.
One specific approach is provided by Y. H. Chang, C. Y. Wu, and T. C. Yu, in an article entitled “Chopper-stabilized sigma-delta modulator,”
IEEE ISCAS
, pp. 1286-1289, May 1993, the disclosure of which is incorporated herein by reference. The chopper stabilized delta-sigma modulator (DSM) with conventional op amps has been shown to have better immunity from low-frequency noise. Unfortunately, the chopping approach also generates residual noise, which comes from the charge-injection mismatch between the switches during the operation of the chopper. The ON and OFF of the switch induce the spikes into the input end of the delta-sigma modulator (DSM). These high-frequency switching noises will track the input signal and enter the modulator, and hence degrade the resolution and SNDR of the system.
Another specific approach is provided by A. Bakker, K. Thiele, and J. H. Huijsing, in an article entitled “A CMOS nested-chopper instrumentation amplifier with 100-nV offset,”
IEEE J. Solid-State Circuits
, vol. 35, no. 12, pp. 1877-1883, December 2000, the disclosure of which is incorporated herein by reference. This article proposes a nested-chopper amplifier to reduce the residual noise. It is believable that if the nested-chopper amplifier is applied to the delta-sigma modulator, the offset of OP AMP and associated low-frequency noise of the modulator can be canceled. However, the front end of the modulator will still suffer from the high-frequency noise caused by the mismatch between the sampling switches.
A further approach is provided by C. B. Wang, in an article entitled “A 20 bit 25 kHz delta-sigma A/D converter utilizing frequency-shaped chopper stabilization scheme,”
IEEE custom integrated circuits conference
, pp. 9-12, 2000, the disclosure of which is incorporated herein by reference. A frequency-shaped chopper stabilized delta-sigma A/D converter is described to remove the clock spike noise. The residual noise is rejected by a random chopper clock. The chopper clock is generated by passing a pseudo-random clock through the digital filter which has two zeros located at DC and half sampling frequency. However, the clock noise will not be exhibited at the interest band.
As will be understood by one skilled in the art, the autozeroing approach of the high-frequency noise, which is sampled by an input switch during a sampling period, will be folding back to the interest band. Consequently, the chopping technique is preferred due to its lower noise than the autozeroing technique in the application of a delta-sigma modulator (DSM).
In view of the foregoing, there is a need for circuitry and methods for reducing the introduction of noise when processing sensitive analog-to-digital conversions of input signals.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills this need by providing a nested-chopper delta-sigma modulator. By using the disclosed circuit and method, the residual noise caused by the mismatch between input chopper switches can be reduced. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, a system, or a device. Several inventive embodiments of the present invention are described below.
In accordance with one aspect of the present invention, a nested chopper circuit is provided. The nested chopper circuit includes a first chopper section, which is coupled to input terminals and is controlled by a pair of non-overlapping clocks. A second chopper section is coupled to the first chopper section, with the output of the first chopper section leading to an input of the second chopper section. A pair of chopper clocks controls the second chopper section. The pair of non-overlapping clocks is a multiple of the pair of chopper clocks, and the non-overlapping clocks are configured to invert on a period continuously.
In one embodiment, the nested chopper circuit is coupled to a delta-sigma modulator (DSM) circuit. In one embodiment, the continuous inverting on the period provides sampling on positive and negative input signals provided to the input terminals of the first chopper section. In one embodiment, the pair of non-overlapping clocks is &phgr;A and &phgr;B and the pair of chopper clocks is &phgr;
11
and &phgr;
12
. In one embodiment, the pair of chopper clocks controls switches S
1
, S
2
, S
3
, and S
4
of the second section. In one embodiment, switches S
1
, S
2
, S
3
, and S
4
follow the following logic when operated in conjunction with the pair of non-overlapping clocks: switches S
1
& S
4
: &phgr;A·&phgr;
11
+&phgr;B·&phgr;
12
; and switches S
2
& S
3
: &phgr;A·&phgr;
12
+&phgr;B·&phgr;
11
.
In another embodiment, the first chopper portion has two outer switches and two inner switches, with the outer switches being controlled by a first non-overlapping clock and the inner switches being controlled by a second non-overlapping clock. In this embodiment, the second chopper section has four switches that are controlled by a pair of chopper clocks. The first and second non-overlapping clocks are each multiples of the pair of chopper clocks. In addition, the first and second non-overlapping clocks are configured to invert on a period continuously, with the inverting of the first non-overlapping clock being in opposite phase from the second non-inverting clock.
In accordance with another aspect of the present invention, a method for chopping an analog input signal for sampling is provided. In this method, an input signal is received. A pair of non-overlapping clocks is provided to a first chopper section. The non-overlapping clocks are configured to invert on a period continuously. A pair of chopper clocks is provided to a second chopper section. The non-overlapping clocks are multiples of the pair of chopper clocks. The input signal is processed through the first chopper section and the second chopper section, and the continuous inverting on the period provides sampling on a positive cycle and a negative cycle of the input signal.


REFERENCES:
patent: 5262686 (1993-11-01), Kurosawa
patent: 5477481 (1995-12-01), Kerth
patent: 5675334 (1997-10-01), McCartney
patent: 5703589 (1997-12-01), Kalthoff et al.
patent: 6285311 (2001-09-01), Lewicki
patent: 6400295 (2002-06-01), Van Herzeele
patent: 6411242 (2002-06-01), Oprescu et al.

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