Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Reexamination Certificate
2002-08-09
2003-11-18
Ngo, Hung V. (Department: 2831)
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
C257S738000, C228S180220
Reexamination Certificate
active
06649833
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an electrical connection between conductors, more particularly to the electrical connection which is comprised of a material which has a negative volume expansion, upon melting and which is lead-free.
BACKGROUND OF THE INVENTION
Solders have been conventionally used for achieving electrical and mechanical joints between electronic devices and electronic parts. Solders containing tin and lead as major components have been generally used for this purpose. In addition, solders not containing lead, so called “lead-free solders”, which typically contain tin as a major component and other metals such as silver and copper are being used in consideration of environmental concerns. In recent years, soldered electronic assemblies with electrical joints having satisfactory soldering characteristics have been produced using such lead-free solders. For example, U.S. Pat. No. 5,730,932, issued on Mar. 24, 1998 and assigned to the IBM Corporation describes a lead-free solder alloy and microelectronics circuits soldered by the alloy. Another example, U.S. Pat. No. 6,204,490 issued on Mar. 20, 2001 and assigned to Hitachi, Ltd., describes a method of manufacturing an electronic circuit card on which components are mounted using a lead-free solder.
Flip chip mounting is an increasingly popular technique for electrically connecting an electronic device, such as an semiconductor chip, to a substrate, such as a circuit board or a chip carrier. In a flip chip configuration, the active circuitry face of the chip is mounted face down or “flipped” onto the substrate. Conductive contact pads on the flip chip are aligned with corresponding conductive contact pads on the substrate, with the flip chip and substrate contact pads electrically connected by way of an electrically conductive material. The flip chip mounting technique eliminates the use of bond wires between a semiconductor chip and substrate, resulting in improved electrical performance.
A wide range of electrically conducting materials have been used for making the electrical connection between conductive contact pads of the flip chip and substrate, the most common of which being solder in the form of bumps. Other materials that have been used to make this connection are gold bumps, gold stud bumps, and electrically conducting polymer compositions.
Once a flip chip is bonded to a substrate, an underfill material is usually dispensed between the flip chip and the substrate. The underfill is typically provided as a liquid adhesive resin and can be dried, cured and/or polymerized. The underfill material provides enhanced mechanical adhesion and mechanical stability between the substrate and the flip chip and inhibits environmental attack of the flip chip and substrate surfaces.
One type of flip chip bonding utilizes what is known as C4 connections (controlled-collapse chip connections) to electrically connect the substrate and the flip chip. C4 interconnections can be arranged in an area array rather than a peripheral array on the face of the flip chip. C4 connections are very small solder bumps formed on the flip chip conductive pads during the processing steps required to manufacture the flip chip module assembly. When the flip chip is placed on the substrate, the solder bumps are aligned with conductive contact pads on the substrate surface substantially arranged in a pattern identical to that of the solder bumps. During a reflow process, the solder bumps melt and wet the conductive pads. The surface tension of the liquid solder helps align the flip chip properly on the substrate. Once the solder is cooled and solidifies, the flip chip is electrically, mechanically, and thermally connected to the substrate. At this point, an underfill material can be dispensed to encapsulate the electrical connections and substantially fill the space between the flip chip and the substrate. The underfill material is then cured to form a flip chip module. During subsequent assembly of the underfilled module to a circuit board or other carrier and during rework, the module can be heated to temperatures that may cause the electrical connections to undergo reflow (to melt). Each reflow operation places stresses on the module, that can have a tendency to cause delamination in the module. Specifically, such delamination refers to delamination at or near the underfill to flip chip interface and/or delamination at or near the underfill to substrate interface. There are three sources of stress manifested during reflow processing which may lead to delamination in the module. These sources of stress are:
1. Coefficient of thermal expansion differences between the materials comprising the layered structure of the module including the flip chip, underfill, solder, and substrate.
2. Steam pressurization of any poorly bonded/adhered underfill interfaces (i.e., partially delaminated interfaces) in this layered region due to vaporization of latent moisture in the module.
3. The melting of the encapsulated solder electrical connection, and the solder volume increase associated with the melting process.
In modules having uniformly good adhesion of the underfill with the flip chip and substrate interfaces, the largest source of stress in the module is the melting of the solder electrical connection and specifically the solder volume increase associated with this melting process. Melting of most commonly used solders results in a volume increase of about 2 to about 4 percent. The volume increase of the solder electrical connection of C4 modules encapsulated by underfill occurs at the solder melting point and, subjects the layered flip chip-underfill-substrate module to large stresses. The molten solder is placed under a large hydrostatic stress by the constraining underfill. Immediately beneath the C4 connections, the stresses are compressive at the flip chip and substrate C4 connection pad interfaces. In the regions immediately adjacent to the C4 connections, the underfill interfaces at the flip chip and substrate are subjected to large delaminating tensile stresses because the molten solder is undergoing an expansion, tending to push the flip chip upwards away from the underfill, while the underfill is expanding at a lesser rate. If the adhesion in these regions is insufficient to withstand the resulting large tensile stresses, delamination results.
The present invention is directed at overcoming the problem associated with the stresses that occur from the solder volume increase associated with the melting process as set forth above. It is desirable to have an electronic package that substantially eliminates this stress. Electronic packages of this type will have lower defect levels and increased operational field life.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly it is the object of this invention to enhance the art of packaging technology.
It is another object of this invention to provide an electrical connection comprising a volume of solder between two conductors that is contractible during melting of the solder.
It is yet another object of this invention to provide an electronic package that provides an improved electrical coupling between a device and a substrate.
Still yet another object of this invention is to provide an electronic package that will be manufactured with relatively lower costs than many current products.
Still yet another object of this invention is to provide an electronic package having at least one solder member electrically coupling a device to a substrate and a dielectric material forming a physical connection between the device and substrate, the volume of the solder member contracting during melting thereof, thereby improving operational field life by preventing failure of the physical connection and/or the electrical connection between the substrate and the device.
According to one aspect of the invention, there is provided an electrical connection comprising a first conductor, a second conductor, and a volume of solder used to form the electrical connection between the first conductor
Caletka David V.
Darbha Krishna
Henderson Donald W.
Lehman Lawrence P.
Thiel George H.
Ngo Hung V.
Samodovitz, Esq. Arthur J.
Scully Scott Murphy & Presser
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