Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1998-07-30
2001-10-16
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C361S093500, C361S111000
Reexamination Certificate
active
06304127
ABSTRACT:
FIELD OF INVENTION
The invention relates to an ESD protection device employing a negative-voltage-trigger SCR.
BACKGROUND OF THE INVENTION
In a Human-Body-Model ESD transient, an 100 PF capacitor is first charged up to an ESD zapping voltage, and then discharges through a 1.5 kohms resistor onto an IC pin. For instance, a zapping voltage level of 2 KV is used to qualify an IC package. The initial peak current is roughly 1.2 A with a rise time of approximately 10 nsec. For integrated circuit packages, the VDD-to-VSS capacitance is typically larger than 1 nF. If the ESD energy is directly absorbed by the power bus, i.e. for ESD stress of VDD pin to VSS pin, or indirectly absorbed by the power bus, i.e. the positive ESD stress on an input or I/O pin that has a pull up device, then the voltage-rising rate inside an IC may reach 1 to 2 volt per nano-second for a Human-Body-Model ESD zapping at 2 to 3 KV level. The pull up device includes p+
well diode or PMOSFET.
Transistors, such as grounded-gate NMOS(GGNMOS), field-oxide MOSFET, output buffer transistors, or bipolar transistors, have been commonly used as primary ESD protection elements for integrated circuits. A Semiconductor Controlled Rectifier (SCR), typically including pnpn junctions, can also be used as primary ESD protection device for protecting an IC pin or a power bus during an ESD event. “ESD in Silicon Integrated Circuits” by A. Amerasekera and C. Duvvury, Chap. 3 and 4, John Wiley & Sons, 1995, provides a basic introduction for an SCR used as an ESD protection device.
FIGS. 1A
,
1
B and
1
C shows the basic structure of an SCR. The anode of an SCR can be connected to an IC pin, while the cathode of the SCR can be connected to ground, for ESD protection of an IC pin. Alternatively, the anode can be connected to VDD bus to prevent the internal circuit from being damaged during an ESD event from the power bus. The conventional SCR is triggered by the nwell to p-substrate junction breakdown, which is relatively high, for instance, typically >20V. This is a drawback when an SCR is used as an ESD protection element since it may not trigger sooner enough during an ESD event to protect other circuit elements from ESD damages.
U.S. Pat. No. 5,465,189 describes an SCR used to provide on-chip protection against ESD stress applied at the input, output, power-supply bus, or between any arbitrary pair of pins of an integrated circuit. A novel structure in the patent having a low breakdown voltage is incorporated into the SCR to lower the trigger voltage of the SCR.
FIG. 2A
shows the low-voltage trigger SCR, according to U.S. Pat. No. 5,465,189, which integrates an NMOSFET with the SCR, such that the trigger voltage of the SCR is equal to the trigger voltage of an NMOSFET, which is typically roughly at or lower than 12 volts.
FIG. 2B
shows a variation of
FIG. 2A
in which an integrated lateral bipolar device, instead of NMOSFET, is provided to reduce the trigger voltage of an SCR.
FIG. 3
shows an example of full-chip ESD protection scheme. The ESD protection of the input pin consists of a resistor R
1
, a diode D
1
pull-up device, a diode D
2
pull-down device. The ESD protection of an output pin relies on the output buffer, e.g. pull-up PMOS and pull-down NMOS, for self protection during an ESD event. Also shown in
FIG. 3
, the VDD bus potential can be pulled high through a pull-up p+
well diode or a pull-up PMOS. And similarly, the VSS bus potential can be pulled low through a pull-down n+/pwell diode or a pull-down NMOS. Therefore, the VDD to VSS voltage difference can be rapidly higher than 10 volt during an ESD events including the following situations: (i) positive stress of VDD pin to VSS pin, (ii) negative stress of VSS pin to VDD pin, (iii) positive stress on an input or I/O pin while the pin is connected to a pull-up (p+nwell) diode or a pull-up PMOS, or (iv) negative stress on an input or I/O pin while the pin is connected to a pull-down (n+/pwell) diode or a pull-down NMOS. Therefore, it is a common practice to include ESD protection elements, such as an SCR device S
1
, between VDD and VSS bus to protect the power bus and the internal circuit from being damaged during an ESD event.
It is of great advantage to lower the trigger voltage of an ESD protection device during an ESD event. As the ESD protection functions sooner, and the transient voltage imposed on the I/O and internal circuit can be lower which provides a better overall ESD protection.
FIG. 4
discloses prior-art methods of negative voltage-pumping which generates a train of negative voltage pulses from positive VDD during circuit operation. As shown in
FIG. 4
, a negative voltage-pump circuit typically comprises at least one pn junction diode D
1
, for clamping the output voltage not to be higher than ground by 0.8 volts, such that a falling-edge clock signal can pump the output voltage to a negative voltage. The capacitor C
1
acts as a capacitive coupling device in FIG.
4
.
SUMMARY OF INVENTION
An electrostatic discharge (ESD) protection structure for an integrated circuit constructed on a substrate of a N type is provided.
The protection structure includes a semiconductor controlled rectifier (SCR) and a transient negative-voltage pumping circuit.
The semiconductor controlled rectifier (SCR) is constructed on the substrate and coupled to the integrated circuit, and the SCR includes a first region of a second type (pwell) formed within the substrate.
The transient negative voltage pumping circuit is coupled to the first region (pwell) while the ESD voltage is applied to the nwell. The transient negative voltage pumping circuit pumps the ESD voltage to a negative voltage during the ESD transient for earlier triggering the SCR during the ESD event.
REFERENCES:
patent: 5670799 (1997-09-01), Croft
patent: 5808342 (1998-09-01), Chen et al.
patent: 5982601 (1999-11-01), Lin
Fulbright & Jaworski L.L.P.
Lam Tuan T.
Nguyen Hiep
Winbond Electronics Corp.
LandOfFree
Negative-voltage-trigger SCR with a stack-gate ESD transient... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Negative-voltage-trigger SCR with a stack-gate ESD transient..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Negative-voltage-trigger SCR with a stack-gate ESD transient... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2555469