Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2003-02-05
2004-10-12
Tra, Quan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S589000
Reexamination Certificate
active
06803807
ABSTRACT:
This nonprovisonal application claims priority under 35 U.S.C. §119 (a) on Patent Application No. 2002-033340 filed in JAPAN on Feb. 12, 2002, which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a negative voltage output charge pump circuit that generates from an input voltage a negative voltage for output.
2. Description of the Prior Art
FIG. 5
is a circuit diagram showing an example of a conventional negative voltage output charge pump circuit. The negative voltage output charge pump circuit
1
a
shown in this figure is so configured that, as a PMOS transistor P
1
and NMOS transistors N
1
, N
2
, and N
3
(all of the enhancement type) acting as switching devices are periodically turned on and off according to control signals S
1
and S
2
, a first capacitor C
1
is charged with an input voltage Vin fed in via an input terminal IN, and then the voltage charged in the first capacitor C
1
is fed out as a negative voltage −Vin via an output terminal OUT.
Now, how a negative voltage is output in the configuration described above will be described in more detail. First, the control signals S
1
and S
2
are fed in so that the PMOS transistor P
1
and the NMOS transistor N
1
are turned on and the NMOS transistors N
2
and N
3
are turned off. When these control signals S
1
and S
2
are fed in, the input voltage Vin is applied to one end (the point A) of the first capacitor C
1
, and the ground potential is applied to the other end (the point B) of the first capacitor C
1
. Thus, the first capacitor C
1
is charged until the potential difference between its terminals becomes equal to the input voltage Vin.
After completion of the charging of the first capacitor C
1
, the logical levels of the control signals S
1
and S
2
are so switched that the PMOS transistor P
1
and the NMOS transistor N
1
are turned off and the NMOS transistors N
2
and N
3
are turned on. As a result of this switching, the point A conducts through the NMOS transistor N
3
to a ground terminal GND, and thus the potential at the point A drops from the level of the input voltage Vin to the ground potential.
Here, as a result of the charging, between the terminals of the first capacitor C
1
appears a potential difference equal to the input voltage Vin, and therefore, when the above-mentioned drop in the potential at the point A occurs, the potential at the point B drops from the ground potential to a negative voltage −Vin. At this time, the point B conducts through the NMOS transistor N
2
to the output terminal OUT, and therefore the electric charge in a second capacitor C
2
moves to the first capacitor C
1
. As a result, the potential at the output terminal OUT drops to the negative voltage −Vin.
In a configuration like the one described above in which MOS transistors are used as switching devices, it is generally necessary to secure a backgate potential for the MOS transistors. The backgate potential of a MOS transistor needs to be lower than its channel potential. This is because, if the backgate potential of a MOS transistor is higher than its channel potential, a PN diode is formed between the backgate and the channel, and permits a current to flow from the backgate to the channel, causing malfunctioning.
For example, in a case where the negative voltage output charge pump circuit
1
a
configured as described above is formed on a p-type substrate so as to have a twin-well structure, all the NMOS transistors N
1
, N
2
, and N
3
are formed on the p-type substrate. Thus, the substrate potential itself serves as the backgate potential. In this case, for the reason mentioned above, the p-type substrate needs to be biased at the lowest potential within the circuit so that the substrate potential is lower than the channel potential of the NMOS transistors N
1
, N
2
, and N
3
.
Here, the lowest potential within the circuit is the potential at the point B as observed when the negative voltage −Vin is generated at the output by the charge in the first capacitor C
1
. However, when the first capacitor C
1
is in the process of being charged, the potential at the point B is equal to the ground potential. That is, the potential at the point B is not always the lowest. Accordingly, in the negative voltage output charge pump circuit la configured as described above, the backgates of the NMOS transistors N
1
, N
2
, and N
3
are connected to the output terminal OUT, at which the negative voltage −Vin is present all the time.
It is true that the negative voltage output charge pump circuit
1
a
configured as described above outputs the desired negative voltage −Vin without the risk of malfunctioning in which currents flow from the backgates of the NMOS transistors to their channels.
However, the negative voltage output charge pump circuit
1
a
configured as described above requires extra operation to bias the p-type substrate at the lowest potential (the negative voltage −Vin at the output terminal OUT) within the circuit. This leads to increased loss of electric power.
Moreover, the negative voltage output charge pump circuit
1
a
configured as described above is prone to malfunctioning caused by a parasitic NPN-type multiple-collector transistor.
FIG. 6
is a vertical sectional view showing an outline of the structure of the negative voltage output charge pump circuit
1
a
formed on a p-type substrate so as to have a twin-well structure.
As shown in this figure, the parasitic NPN-type transistors Q
1
has its emitter at the point B, has its base at the p-type substrate SUB, and has its collectors at the n-type well of the PMOS transistor P
1
and the source of the NMOS transistor N
1
.
When the potential at the output terminal OUT and the potential at the p-type substrate SUB are made low, the potential at the point B, which is the emitter of the parasitic NPN-type transistors Q
1
, drops to the level of the negative voltage −Vin. At this time, the p-type substrate SUB, which is the base of the parasitic NPN-type transistors Q
1
, is at the ground potential. Accordingly, the base-emitter section of the parasitic NPN-type transistors Q
1
is forward-biased, permitting a current to flow from the collector to the emitter.
When this unintended current flows to the point B, it captures the electric charge that is supposed to be fed to the first capacitor C
1
to generate the negative voltage −Vin. As a result, neither the potential at the p-type substrate SUB nor the potential at the output terminal OUT drops, and thus no negative voltage is generated. This is because the current that flows from the p-type substrate SUB to the point B corresponds to the base current of the parasitic NPN-type transistors Q
1
, and thus hfe times that current flows to the point B. Moreover, the potential at the n-type well W, which is one of the multiple collectors of the parasitic NPN-type transistors Q
1
, is higher than the potential at the output terminal OUT and the potential at the p-type substrate SUB, and this causes an accordingly large current to flow to the point B.
The above-described malfunctioning caused by the parasitic NPN-type transistors Q
1
can be overcome by replacing the NMOS transistors N
1
and N
2
, to which a negative voltage is applied, both with PMOS transistors.
FIG. 7
is a circuit diagram showing another example of a conventional negative voltage output charge pump circuit. When the negative voltage output charge pump circuit
1
b
shown in this figure is formed on a p-type substrate so as to have a twin-well structure, PMOS transistors P
1
, P
2
, and P
3
are formed on an n-type well electrically separated from the p-type substrate, and the backgate of the n-type well is connected to a potential higher than that of its channel (in the figure, to the input voltage Vin).
It is true that the negative voltage output charge pump circuit
1
b
configured as described above causes no serious problem even when the potential at the above-mentioned channel drops to the level of
Doi Hiroki
Fujiyama Toshiya
Inamori Masanori
Birch & Stewart Kolasch & Birch, LLP
Sharp Kabushiki Kaisha
Tra Quan
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