Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1999-04-15
2001-05-22
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S089000, C327S563000, C330S253000
Reexamination Certificate
active
06236243
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a level detecting circuit. More particularly, the invention relates to a negative voltage level detecting circuit to be used for writing operation or erasure operation for a flash memory.
2. Description of the Related Art
In writing operation or erasure operation for a flash memory as a non-volatile memory, it is becoming a trend to use a negative voltage in combination with a positive voltage in order to realize operation at low potential. In a transformer circuit for generating the negative voltage to be used for such purpose, it is important to stably control the output voltage thereof in a wide power source voltage range.
One example of the conventional negative voltage level detecting circuit to be used for such control has been disclosed in Japanese Unexamined Patent Publication No. Heisei 6-68690. Such a circuit will be briefly discussed with reference to
FIGS. 4A and 4B
.
In
FIG. 4A
, a level detecting circuit
10
is constructed with a level shifter
1
for inputting a voltage Vn from a negative voltage generating circuit, and a signal amplifier portion
2
for switching a voltage level at a node N
0
depending upon an output of the level shifter
1
.
The level shifter
1
shown in
FIG. 4A
is constructed with including a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) TN
2
, p-MOSFET TP
2
and p-MOSFET TP
3
.
On the other hand, the signal amplifier portion
2
is constructed with p-MOSFET TP
1
and n-MOSFET N
1
. The signal amplifier portion
2
receives the output of the level shifter
1
and detects that the voltage Vn is lowered in order to be lower than a desired voltage level Vx (namely, voltage Vn≦Vx) (time tx) to switch the voltage at the node N
0
from a high level (substantially equal value to a power source voltage Vcc) of a binary signal to a low level (approximately 0V).
The voltage appearing at the node N
0
is normally input to a logic gate such as an inverter INV or the like for wave shaping and is transformed into a complete CMOS (Complementary Metal Oxide Semiconductor) logic level signal. This logic level signal is illustrated as signal OUT in FIG.
4
B.
On the other hand, in
FIG. 4B
, when the voltage Vn>Vx, a drain-source voltage of the n-MOSFET TN
2
becomes sufficiently high to turn ON the n-MOSFET TN
1
, ON-resistance of the p-MOSFET TP
1
becomes smaller than ON-resistance of the n-MOSFET N
1
. Therefore, the voltage of the node N
0
becomes high level (signal OUT is GND level). On the other hand, when voltage Vn≦Vx is established, the drain-source voltage of the n-MOSFET TN
2
becomes sufficiently high to turn ON the n-MOSFET TN
1
, ON-resistance of the n-MOSFET TN
1
becomes smaller than ON-resistance of the p-MOSFET TP
1
. Therefore, the voltage of the node N
0
becomes low level (signal OUT is the power source voltage Vcc level).
In the foregoing circuit, voltage level detection (detection signal generation) is performed with ON-resistance ratio of the n-type MOSFET and the p-type MOSFET, and a voltage amplification degree of the signal amplifier portion
2
is low. Therefore, output (voltage at the node N
0
) inverting operation of the signal amplifier portion
2
is slow to slow-down the operation speed. On the other hand, a problem is encountered in that an inverting period (tx) significantly depends on fluctuation of the power source voltage or device characteristics.
It should be noted that Japanese Unexamined Patent Publication No. Heisei 5-175801 also discloses a circuit including the level shifter and the signal amplifier portion. However, in the circuit disclosed in the above-identified publication, it concerns the power source voltage level (positive voltage) to be supplied to a memory chip. The foregoing drawback is directed to a problem in that the voltage level (negative voltage) generated within the memory chip by the transformer circuit. Accordingly, in the content of disclosure of the above-identified publication, the foregoing problem cannot be solved.
SUMMARY OF THE INVENTION
The present invention has been worked out for solving the drawbacks in the prior art as set forth above. Therefore, it is an object of the present invention to provide a level detecting circuit which can operate stably at high speed and low voltage irrespective of fluctuation of power source voltage and tolerance in the device, in output level detection of a transformer circuit for generating a negative voltage to be used for a flash memory or so forth.
In order to accomplish the above-mentioned and other objects, a level detecting circuit, according to one aspect of the present invention, comprises:
level shifting means for performing predetermined level shifting of a voltage level of an input signal input from a load voltage generating circuit, with a resistance type potential division by a voltage dividing resistor element using a reference power source voltage independent of a power source voltage to be supplied to own circuit, and
differential amplifier feeding an output depending upon a difference between a level shifted signal from the level shifter and a predetermined reference voltage for leading an output thereof as a detection output.
In the preferred construction, the voltage dividing resistor elements in the level shifting signal may be connected in series between the reference power source voltage independent of the power source voltage to be supplied to own circuit, and the level shifted signal may be led from one end of the series connected resistor elements. The level shifting means may perform level shifting of the input signal so that a voltage level of the input signal becomes the predetermined reference voltage at a predetermined voltage level.
On the other hand, the differential amplifier may include a pair of transistors forming a differential pair and a current mirror circuit to be a load for the pair of transistors, and the detection output may be lead from a junction between the transistors and the current mirror circuit. In this case, the differential amplifier may further include a constant current source, and the pair of transistors may be provided between the constant current source and the current mirror circuit.
The differential amplifier may have a transistor to be a constant current source to be controlled to ON condition by a constant voltage independent of the power source voltage supplied to the own circuit, the pair of transistors may be provided between the transistor and the current mirror circuit.
The level detecting circuit may further comprise another transistor which is turned ON depending upon the output of the transistor, in parallel to the transistor. The predetermined reference voltage may be equal to a grounding potential.
The level detecting circuit may further comprise a logical level transforming means for transforming the detection output into a CMOS logic level signal. The logic level transforming means may be an inverter circuit constructed with a CMOS logic circuit.
The voltage dividing resistor element may be formed of a polycrystalline silicon. In the alternative, the voltage dividing resistor element may be formed with a combination of MOSFETs.
REFERENCES:
patent: 5194762 (1997-05-01), Hara et al.
patent: 5627493 (1997-05-01), Takeuchi et al.
patent: 63-70609 (1988-03-01), None
patent: 5-175801 (1993-07-01), None
patent: 6-68690 (1994-03-01), None
patent: 8-237103 (1996-09-01), None
McGinn & Gibb PLLC
NEC Corporation
Wells Kenneth B.
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