Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Utilizing three or more electrode solid-state device
Patent
1993-08-31
1995-03-21
Wambach, Margaret R.
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Utilizing three or more electrode solid-state device
36518909, 327536, 327589, 326 92, H03K 1901, H03K 301
Patent
active
053999282
DESCRIPTION:
BRIEF SUMMARY
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is related to co-pending U.S. patent application entitled NON-VOLATILE MEMORY CELL AND ARRAY ARCHITECTURE, Ser. No. 07/823,882, filed Jan. 22, 1992, which was owned at the time of invention and is currently owned by the same assignee.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to negative voltage generators responsive to positive voltage power supplies, and more particularly, to providing high negative voltages in integrated circuits such as FLASH EPROM memory devices.
2. Description of Related Art
Different levels of internal voltage are required during various modes of operation of FLASH EPROM (electrically programmable read only memory) integrated circuits for electrically erasing, programing or reading a memory cell. The memory cells in FLASH EPROM are formed using so-called floating gate transistors in which the data is stored by charging or discharging the floating gate.
The act of charging the floating gate is termed the program mode for a FLASH EPROM. This is typically accomplished using hot electron injection induced by establishing a large positive voltage between the gate and source, as much as 12 volts, and a positive voltage between the drain and source, for instance, 7 volts.
The act of discharging the floating gate is called the erase mode for a FLASH EPROM. This erase function is typically carried out through Fowler-Nordheim tunneling induced by establishing a large positive voltage from the source to gate, while floating the drain of the memory cell. This positive voltage can be as much as 12 volts.
However, when applying 12 volts to the source and grounding the gate, very high reverse voltage is developed between source and substrate, the generation of hot holes is increased, and the memory cell may exhibit "hot hole trapping." Hot hole trapping degrades endurance cycling performance of the device.
In order to alleviate hot hole trapping during an erase operation, a negative voltage may be applied to the gate of the memory cell. Instead of applying 12 volts to the source and grounding the gate, a large negative voltage, such as less then -7.5 volts, may be applied to the gate and a lower positive voltage may be applied to the source, for example, 7.0 volts. Thus, much lower voltages are developed between the source and substrate and hot hole generation is suppressed.
However, FLASH EPROM memory is typically supplied with two external positive power sources rather than a negative power supply. The first positive power source, V.sub.DD, is applied at power up and is typically used during the read operation. V.sub.DD is usually 5.0.+-.0.5 volts. The second positive power source, V.sub.PP, is typically applied during program or erase mode, and is typically 12.0.+-.0.6 volts. Therefore, in order to supply negative voltage to the EPROM cells, a relatively large negative voltage must be generated from either of the two positive power supplies.
Therefore, it is desirable to provide a circuit used in supplying a relatively precise high negative voltage without regulation, to FLASH EPROM memory cells, or other environments relying on positive power supplies from a positive power supply.
SUMMARY OF THE INVENTION
The present invention provides a circuit for generating negative voltage in an integrated circuit, in response to a positive voltage source. In particular, a FLASH EPROM integrated circuit, according to the present invention, presents a negative voltage generator responsive to high positive programming potential V.sub.PP to supply a negative voltage.
According to one aspect of the present invention, the circuit for providing negative voltage is based on a charge pump driven by a periodic signal oscillating between essentially ground and a positive potential. The charge pump includes a first capacitor having a first terminal means receiving the positive periodic signal. The second terminal of the capacitor is clamped to a reference potential near ground, so that the second terminal
REFERENCES:
patent: 5222040 (1993-06-01), Challa
patent: 5235544 (1993-08-01), Caywood
patent: 5287536 (1994-02-01), Schreck et al.
patent: 5321653 (1994-06-01), Suh et al.
patent: 5329168 (1994-07-01), Sugibayashi et al.
Chao Liang
Lin Tien-Ler
Macronix International Co. Ltd.
Wambach Margaret R.
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