Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-05-28
2001-06-12
Phan, Trong (Department: 2818)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C365S226000
Reexamination Certificate
active
06246280
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a voltage generating circuit responsive to a reference voltage for outputting a negative voltage and, particularly to a structure of a voltage generating circuit with high control responsiveness for a voltage while ensuring an operation reliability of a transistor in the voltage generating circuit. The present invention also relates to a semiconductor memory device using the voltage generating circuit for driving a word line.
2. Description of the Background Art
Recently, an instrument driven by a battery such as a portable personal computer or information terminal instrument is widely used. Thus, reduction in power consumption of a semiconductor memory, that is, at a low voltage operation, is required.
A size of a transistor is on the decrease due to development in fine patterning of the transistor with increase in a capacity of a semiconductor memory. In this respect, the low voltage operation is an indispensable requirement to ensure a reliability of the operation of the transistor.
In this context, a relation between an operating voltage (Vcc) and a threshold voltage (Vt) of the transistor is becoming important. Generally, an operation speed of a transistor is in inverse proportion to a difference between a power supply voltage and a threshold voltage, that is, Vcc−Vt. Thus, threshold voltage Vt must be decreased to ensure a sufficient speed with the low voltage operation.
However, as threshold voltage Vt decreases, a subthreshold current in a cut-off region increases. In a dynamic random access memory (which is hereinafter abbreviated as DRAM) which is used as a general-purpose product, data holding time is preliminary defined as a specification. The aforementioned problem has a significant impact on a transistor especially used for a memory cell of a DRAM. More specifically, increase in a leakage current results in reduction in the data holding time, and therefore it is extremely difficult to allow threshold voltage (Vt) to be freely decreased with decrease in operating voltage (Vcc).
For sufficiently writing data at an “H” level to a memory cell, a maximum word line voltage corresponding to a selection state (“H” level) of the word line which is connected to a gate of an access transistor of the memory cell must be set at Vcc+Vt or higher. Thus, threshold voltage (Vt) must be set at a low value in order to ensure a reliability of the gate oxide film of a fine patterned transistor.
As described above, setting of threshold voltage (Vt) of the transistor is extremely difficult with such requirement for the low voltage operation of the semiconductor memory.
To solve this problem, a structure of a word line which is driven by a negative voltage has been proposed as shown in “Low Voltage Circuit Design Techniques for Battery-Operated and/or Giga-Scale DRAM's”, by T. Yamagata et al.,
IEEE Journal of Solid
-
State Circuits,
1995, pp. 1183-1188 (which is hereinafter called as a first conventional art).
In the first conventional art, a maximum word line voltage (that is a voltage applied to a gate of a transistor of a memory cell) required for writing data at the “H” level is decreased by decreasing a threshold voltage of the transistor of the memory cell, so that reliability of the transistor is ensured. At the same time, a negative voltage is applied to the word line when holding data to prevent leakage of a subthreshold voltage, so that a sufficient data holding time is ensured.
To implement the structure, stability of the negative voltage applied to the word line when holding data is very important. The subthreshold current causing leakage increases by about ten times if a gate voltage increases by 0.1V. Thus, a voltage generating circuit capable of supplying a negative voltage with high accuracy is required for driving the word line.
A structure has been proposed as a negative voltage generating circuit with accuracy which can be used for this purpose in “A Precise On-Chip Voltage Generator for a Giga-Scale DRAM with a Negative Word-Line Scheme”, by H. Tanaka et al., 1998
Symposium on VLSI Circuits Digest of Technical Papers
, pp. 94-95 (which is hereinafter called as a second conventional art).
FIG. 9
is a schematic block diagram showing an overall structure of a voltage generating circuit
500
of the second conventional art.
Referring to
FIG. 9
, voltage generating circuit
500
includes: a charge pump regulator
530
outputting a negative voltage Vbb to a line
532
; a differential amplifier
510
comparing a reference voltage Vrn and an output voltage Vnn and amplifying a difference therebetween for output; and an N channel transistor
520
responsive to an output from differential amplifier
510
for controlling an amount of electric charges supplied for a line
533
transmitting output voltage Vnn from the line
532
.
Voltage generating circuit
500
is applied to a semiconductor memory device, and generates output voltage Vnn(−0.75V) used for driving a word line when holding data and Vbb(−1.0V) used as a voltage for back bias of a semiconductor substrate.
An exemplary circuit structure of charge pump regulator
530
is shown, for example, in
Ultra LSI Memory
(by Kiyoo Ito, Baifukan) pp. 241-242.
FIG. 10
is a circuit diagram showing an exemplary structure of charge pump regulator
530
.
Referring to
FIG. 10
, charge pump regulator
530
includes a self-oscillator
540
and a charge pump circuit
550
. Self-oscillator
540
generates a pulse signal at a frequency f
1
with two states of “H” level (Vcc) and “L” level (GND).
Charge pump circuit
550
includes: an output node Ne; an intermediate node Nb; a charge capacitor C
1
receiving an output from self-oscillator
540
and connected to intermediate node Nd; a transistor Q
1
for rectification connected between intermediate node Nd and a ground line; and a transistor Q
2
for rectification connected between intermediate node Nd and output node Ne. There is a parasitic capacitance C
2
(C
1
>>C
2
) between intermediate node Nd and the ground line.
Voltage Vbb generated at output node Ne is applied to a substrate (a substrate capacitance C
SUB
) as a back bias voltage. Consumed substrate current is indicated by a current source (Ibb) connected in parallel to substrate capacitance C
SUB
.
In charge pump circuit
550
, a voltage in pulse (with amplitude of Vcc) is periodically applied to the capacitance of charge capacitor C
1
, and transistor Q
1
or transistor Q
2
is turned on in accordance with a potential at intermediate node Nd. Thus, electrons stored in charge capacitor C
1
are supplied for a load (substrate capacitance C
SUB
) until output voltage Vbb at node Ne reaches a maximum negative voltage Vnmin=−Vcc+Vt
1
+Vt
2
(Vt
1
: threshold voltage of transistor Q
1
, Vt
2
: threshold voltage of transistor Q
2
).
Conversely, when back bias voltage Vbb is externally applied, a current supplying ability of charge pump regulator
530
is represented by a product of &Dgr;V(&Dgr;V=Vbb−Vnmin), which is a difference between the above mentioned maximum negative voltage Vnmin and output voltage Vbb, a capacitance value of the charge capacitor and frequency f of the self-oscillator (C
1
·&Dgr;V·f).
Body regions of transistors Q
1
and Q
2
included in charge pump circuit
550
are connected to output node Ne, and transistors Q
1
and Q
2
are also back biased by output voltage Vbb. Thus, a voltage at Vcc−Vbb at maximum is applied to a gate oxide film of transistor Q
1
.
Voltage generating circuit
500
maintains output voltage Vnn at reference voltage Vrn by driving differential amplifier
510
by voltage Vbb at an output node of charge pump regulator
530
and a power supply voltage Vcc, controlling an amount of current through a current path formed in transistor
520
in accordance with an output from differential amplifier
510
and supplying electric charges necessary for the line
533
. Voltage generating circuit
500
is characterized i
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Phan Trong
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