Static information storage and retrieval – Floating gate – Particular biasing
Patent
1995-03-24
1996-08-20
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
36518523, 36518527, G11C 700
Patent
active
055485510
ABSTRACT:
A negative voltage decoder applies a negative voltage to the sense line of a selected row of a memory array but not to sense lines of unselected rows. The negative voltage decoder includes a negative voltage source, an array of P-channel transistors, and a negative voltage address signal generator. P-channel transistors in the array have gates coupled to address lines, so that address signals on the address lines turn on the P-channel transistors and connect only the selected sense line to the negative voltage source. A negative voltage charge pumps in the negative voltage address signal generator generates address signals lower than the negative voltage source. In one embodiment, the transistor array has rows of P-channel transistors which fit the pitch of the memory array and individual P-channel transistors which are stacked laterally away from the memory array, and each row of P-channel transistors couples through a set of individual transistor to a set of sense lines. When a positive voltage decoder applies a positive voltage to the sense lines, the negative voltage address signal generator provides a high voltage to shut off the transistors directly coupled to the sense lines. An isolation circuit isolates the positive voltage row decoder from the negative voltage applied by the negative voltage decoder.
REFERENCES:
patent: 5309402 (1994-05-01), Okazawa
patent: 5406517 (1995-04-01), Chang et al.
Gupta Anil
Randhawa Hiten D. S.
Wang Chi-Ming
Catalyst Semiconductor Corp.
Heid David W.
Le Vu A.
Millers David T.
Nelms David C.
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