Negative resistance device

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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357 23, 357 51, 357 57, 357 86, 307291, H01L 2702

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active

043843000

ABSTRACT:
A negative resistance device utilizing a substrate bias effect is comprised of two MOS transistors of n-channel type and p-channel type. The two transistors are connected at the sources and the gates. The drain of the n-channel MOS transistor is connected to the substrate of the p-channel MOS transistor. The drain of the p-channel MOS transistor is connected to the substrate of the n-channel MOS transistor.

REFERENCES:
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patent: 4064525 (1977-12-01), Kano et al.
patent: 4231055 (1980-10-01), Iizuka
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A. Nguyen-Huu, "Advances in CMOS Dev. Tech.," Comput. Design, vol. 14, #1, Jan. 1975, pp. 87-92.
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A. Ipri, "Lambda Diodes Util. An Enhance-Depl. CMOS/SOS Proc." IEEE Trans. on Elec. Dev., vol. ED-24, #6, Jun. 1977, pp. 751-756.

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