Negative R-S triggered latch

Details Negative R-S triggered latch Negative R-S triggered latch

1976-07-08

1977-08-30

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307215, 307247R, 328195, 328196, 328206, H03K 3286

Patent

active

040456935

ABSTRACT:
A negative, edge-triggered R-S latch, which provides predetermined output states for any and all R-S inputs, may be obtained by using an AND-OR-Invert (A-O-I) circuit in conjunction with a "D"-type flip-flop. The reset input and the Q-output of the flip-flop provide the inputs to one AND-gate of the A-O-I circuit. The set input and Q-output of the flip-flop provide the inputs to the other AND-gate. The output of the A-O-I provides the clock input to the flip-flop. The Q-output is also connected to the D-input of the flip-flop.

REFERENCES:
patent: 3001140 (1961-09-01), Beck
patent: 3467839 (1969-09-01), Miller
patent: 3508079 (1970-04-01), Moll et al.
patent: 3845325 (1974-10-01), Daniels et al.
patent: 3895240 (1975-07-01), Kawagoe
patent: 3976949 (1976-08-01), Hepworth et al.

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