Negative input voltage CMOS circuit

Details Negative input voltage CMOS circuit Negative input voltage CMOS circuit

1985-04-15

1987-03-03

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307296R, 307297, 307304, H03K 19094, H03K 1920, H03K 3353

Patent

active

046477985

ABSTRACT:
A CMOS inverter circuit wherein the input device is formed with a p-well as the back-gate and is adapted to receive negative going input signals at the p-well. The gate of the input device is connected to a bias supply set just above the threshold for the input device. With the input signal voltage at 0, the inverter is on, and the output voltage is near 0. As the input signal voltage goes negative, the threshold of the input device increases due to the back-gate bias effect, and it turns off, causing the output voltage to go positive.

REFERENCES:
patent: 3702943 (1972-11-01), Heuner et al.
patent: 4259686 (1981-03-01), Suzuki et al.
patent: 4326136 (1982-04-01), Le Can et al.

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