Amplifiers – With semiconductor amplifying device – Including gain control means
Reexamination Certificate
2000-07-10
2002-09-17
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including gain control means
C330S282000
Reexamination Certificate
active
06452452
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to transistor amplifier circuits, such as, but not limited to FET or bipolar transistor amplifier circuits those that may be employed in RF power amplifiers, and is particularly directed to using a negative feedback-based mechanism for electronically controlling the forward loop gain of a common electrode (e.g., emitter or source) transistor without affecting its operating point.
BACKGROUND OF THE INVENTION
Because linearity is a relatively important criterion in the successful operation of RF communication circuits, a common input/output electrode-connected transistor circuit is frequently used as the basic building block of the amplifier architecture.
FIG. 1
shows a reduced complexity illustration of a common emitter-configured bipolar transistor Q
1
having its base
11
coupled to an input terminal
21
to which a signal to be amplified is applied. The transistor's emitter
12
is coupled to a reference (ground) terminal, and its collector
13
is coupled to an output terminal
22
from which an amplified RF output signal is derived.
In the circuit architecture of
FIG. 1
, the gain of the amplifier is established by the value of a resistor
23
coupled in a feedback path from the collector
13
to the base
11
. In order to vary the gain of the amplifier, it is common practice to intercouple the common emitter transistor Q
1
with one or more control circuits, which typically provide some form of bias current modulation or emitter degeneration.
For example,
FIG. 2
diagrammatically illustrates a multistage architecture of the type described in the U.S. Patent to Leidich, U.S. Pat. No. 4,305,044, having a common emitter transistor T
1
cascaded with a common collector transistor T
3
. An input signal to be amplified is coupled to the base of the first stage, common emitter transistor T
1
via an input terminal
10
, while the amplified output signal is derived from an output terminal
16
connected to the emitter of the second stage, common collector transistor T
3
. A gain control voltage is applied via a terminal
14
to the base of a bias current control transistor T
2
, the collector of which is connected via node
18
to the collector of a common emitter transistor T
1
and the base of the transistor T
3
. This gain control voltage serves to modulate the conductance (gm) and thereby the collector current of the common emitter amplifier transistor T
1
.
Other examples of gain controlled common emitter transistor circuit include those disclosed in the U.S. Pat. Nos. 3,903,479; 3,942,129; 4,048,576; 4,275,362; 4,365,208; and 4,727,335. A common shortcoming of these amplifier designs is the fact that the gain of the common electrode (e.g., emitter) transistor stage is varied by changing its operating point. Because the amplifier's linearity is tightly linked to its operating point, changing its gain in this manner undesirably modulates its linearity.
SUMMARY OF THE INVENTION
Pursuant to the present invention, shortcomings of prior art gain control mechanisms for common electrode transistor amplifiers, described above, in particular the unwanted variation in the transistor's operating point, are effectively obviated by a new and improved single stage common electrode transistor amplifier architecture, having an auxiliary electronically controllable conductance installed in a negative feedback path between a first input/output electrode (e.g., collector in the case of a bipolar transistor, drain in the case of a FET) and a control electrode (e.g., base in the case of a bipolar transistor, gate in the case of a FET).
In a first embodiment of the invention applied to a bipolar, common emitter circuit for purposes of providing a non-limiting example, the electronically controlled conductance comprises a diode, whose forward conductance is adjustable by a controllable current source/sink. By varying the amount of current flowing through the controllable current source, the amount of current flowing through diode and thereby its conductance for defining the amount of feedback from the collector to the base and thus the forward loop gain of the common emitter transistor may be varied. Since the bias conditions for the common emitter transistor are unaffected by this control of the conductance of the diode, the operating point of the transistor remains constant, as its gain is controllably varied.
In a second embodiment of the invention (again using a bipolar transistor as a non-limiting example), the electronically controlled conductance comprises a common collector-configured, emitter-follow transistor, having its base coupled to the collector of the common emitter transistor, and its emitter coupled to the base of the common emitter transistor. The gain of the emitter-follower transistor is controlled by coupling its emitter to a controllable current source/sink. varying the amount of current through the controllable current source varies the base-emitter current through the emitter-follower transistor, so that the its voltage follower transfer function, namely the voltage fed back from the collector to the base of the common emitter transistor is varied with the current source current. As in the first embodiment, varying the current source varies the operating point of the feedback device - here, the emitter-follower transistor. However, the bias conditions for the common emitter transistor remain unaffected, so that the operating point and thereby the linearity of the common emitter transistor remain constant, as its gain is controlled. Advantageously, the auxiliary conductance employed in each embodiment has an electronically controlled PN junction device structure of the type contained in the common emitter bipolar transistor circuit, which eliminates the need for an additional mask set in the processing sequence used to fabricate the amplifier circuit.
REFERENCES:
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patent: 3942129 (1976-03-01), Hall
patent: 4048576 (1977-09-01), Blackburn et al.
patent: 4275362 (1981-06-01), Harford
patent: 4305044 (1981-12-01), Leidich
patent: 4365208 (1982-12-01), Harford
patent: 4727335 (1988-02-01), Yokoyama
patent: 4774478 (1988-09-01), Taylor
patent: 5264806 (1993-11-01), Kobayashi
patent: 5389896 (1995-02-01), Kobayashi
patent: 5525929 (1996-06-01), Nagahori et al.
patent: 5661437 (1997-08-01), Nishikawa et al.
patent: 5914640 (1999-06-01), Nasserbakht
patent: 6057736 (2000-05-01), Kim et al.
Alllen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
Intersil America's Inc.
Nguyen Khanh Van
Pascal Robert
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