Negative feeback control of dummy row electrodes to reduce cross

Details Negative feeback control of dummy row electrodes to reduce cross Negative feeback control of dummy row electrodes to reduce cross

1995-09-08

1998-06-02

Powell, Mark R.

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

G09G 336

Patent

active

057607575

ABSTRACT:
To eliminate or suppress the effect of inductance from changes in signal electrode potential on scan electrode potential due to liquid crystal static capacitance, dummy electrodes DH, DM, and DL have virtually the same construction as a scan electrode X, and are crossed with signal electrodes Y1.about.YM, sandwiching the liquid crystal. The output terminals of operational amplifiers 20, 22, and 24 are respectively coupled to dummy electrodes DH, DM, and DL through output buffer transistors 26H, 26M, and 26L, while at the same time being coupled to each scan electrode X.sub.i through output buffer transistor 28H(i), 28M(i), and 28L(i). Dummy electrodes DH, DM, and DL are respectively coupled to the inverting input terminals of operational amplifiers 20, 22, and 24.

REFERENCES:
patent: 5434599 (1995-07-01), Hirai et al.
patent: 5489910 (1996-02-01), Kuwata et al.
patent: 5576729 (1996-11-01), Yamazaki

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