Negative charge pump circuit for electrically erasable semicondu

Details Negative charge pump circuit for electrically erasable semicondu Negative charge pump circuit for electrically erasable semicondu

1996-10-31

1998-05-19

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 327536, 327540, G11C 1604

Patent

active

057544760

ABSTRACT:
A negative charge pump circuit having a plurality of charge pump stages. Each charge pump stage has an input node and an output node and includes a pass transistor and a first coupling capacitor. The pass transistor has a first terminal connected to the input node, a second terminal connected to the output node and a control terminal connected to an internal node of the charge pump stage. The first coupling capacitor has a first plate connected to said output node and a second plate connected to a respective clock signal. Negative voltage regulation means are provided for regulating a negative output voltage on an output node of the negative charge pump circuit to provide a fixed negative voltage value. The negative charge pump circuit includes at least one negative voltage limiting means electrically coupling said output node of the negative charge pump circuit with the internal node of the last charge pump stage of the negative charge pump circuit. The negative voltage limiting means limits the negative voltage on the internal node and on the output node of said last charge pump stage.

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