Near chip scale package integration process

Details Near chip scale package integration process Near chip scale package integration process

2007-10-25

2010-11-02

Smith, Matthew S (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C257SE21502, C257SE23116

Reexamination Certificate

active

07824965

ABSTRACT:
Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die.

REFERENCES:
patent: 4710798 (1987-12-01), Marcantonio
patent: 4918811 (1990-04-01), Eichelberger et al.
patent: 5019997 (1991-05-01), Haller
patent: 5049978 (1991-09-01), Bates et al.
patent: 5359496 (1994-10-01), Kornrumpf et al.
patent: 5637916 (1997-06-01), Joshi
patent: 5841193 (1998-11-01), Eichelberger
patent: 5990553 (1999-11-01), Morita et al.
patent: 6159767 (2000-12-01), Eichelberger
patent: 6239482 (2001-05-01), Fillion et al.
patent: 6388335 (2002-05-01), Lam
patent: 6396148 (2002-05-01), Eichelberger et al.
patent: 6426545 (2002-07-01), Eichelberger et al.
patent: 6555908 (2003-04-01), Eichelberger et al.
patent: 6818544 (2004-11-01), Eichelberger et al.
patent: 6856007 (2005-02-01), Warner
patent: 7160756 (2007-01-01), Kripesh et al.
patent: 7553699 (2009-06-01), Lee
patent: 7619901 (2009-11-01), Eichelberger et al.
patent: 2005/0158009 (2005-07-01), Eichelberger et al.
patent: 08148620 (1996-06-01), None

Affiliated with

Also associated with

Rating

Near chip scale package integration process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Near chip scale package integration process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Near chip scale package integration process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4215666