Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1999-08-26
2002-02-19
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S014000, C438S734000
Reexamination Certificate
active
06348364
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to semiconductor device assemblies, and more particularly to techniques for analyzing and debugging circuitry associated with integrated circuits such as those accessible from their backsides.
BACKGROUND OF THE INVENTION
In recent years, the semiconductor industry has realized tremendous advances in technology which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
There have been a number of semiconductor dies and packaging types used to address these needs for increased numbers of external electrical connections. For example, to increase the number of pad sites available for a die, especially for multi-layer type dies, an increasingly popular packaging technique called controlled collapse chip connection or flip-chip packaging has been developed. In this technology, the bonding pads are provided with metal (solder) bumps. The bonding pads need not be on the periphery of the die and hence are moved to the site nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter. Electrical connection to the package is made when the die is flipped over the package with corresponding bonding pads and soldered. Once a flip-chip die is attached to the package, the backside portion of the die remains exposed. As a result, the dies are often referred to as “flip-chip” devices. Each bump connects to a corresponding package inner lead. The packages that result are lower profile and have lower electrical resistance and a shortened electrical path.
The output terminals of such packages vary, depending on the package type. For example, some output terminals are ball-shaped conductive bump contacts (usually solder, or other similar conductive material), and they are typically disposed in a rectangular array. These packages are occasionally referred to as “Ball Grid Array” (BGA). Another type of package, commonly known as pin grid array (PGA) package, implements the output terminals as pins.
For BGA, PGA and other types of packages, once the die is attached to the package, the backside portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially grown silicon layer on a single crystal silicon wafer from which the die is singulated. The side of the die including the epitaxial layer containing the transistors, and the other active circuitry is often referred to as the circuit side of the die or front side of the die. The circuit side of the die is positioned very near the package. The circuit side opposes the backside of the die. Between the backside and the circuit side of the die is single crystalline silicon. The positioning of the circuit side provides many of the advantages of the flip-chip.
In some instances the orientation of the die with the circuit side face down on a substrate may be a disadvantage or present new challenges. For example, when a circuit fails or when it is necessary to modify a particular chip, access to the transistors and circuitry near the circuit side is typically obtained only from the backside of the chip. This is challenging since the transistors are in a very thin layer (about 10 micrometers) of silicon buried under the bulk silicon (greater than 500 micrometers). Thus, the circuit side of the flip-chip die is not visible or accessible for viewing using optical or scanning electron microscopy.
Techniques have been developed to access the circuit even though the circuitry of the integrated circuit (IC) is buried under the bulk silicon. For example, infrared (IR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. However, because of the absorption losses of IR radiation in silicon, it is generally required to thin the die to less than 100 microns in order to view the circuit using IR microscopy. On a die that is 725 microns thick, this involves removing at least 625 microns of silicon before IR microscopy can be used.
Thinning the die for failure analysis of a flip-chip bonded IC is usually accomplished in two or three steps. First, the backside of the die is thinned across the whole die surface. This is also referred to as global thinning. Global thinning is done to allow viewing of the active circuit from the backside of the die using IR microscopy. Mechanical polishing is one method for global thinning. Second, using IR microscopy, an area is identified for accessing to a particular area of the circuit. In connection with the second step and typically before the underlying circuitry is analyzed, a third step involves local thinning an access path (or hole) to further thin a specific region that is less than the whole die surface of the silicon.
Using the above process to accurately locate and access underlying circuitry is not always straight forward. For instance, when forming an access hole of this type, it is often difficult to navigate so that the access hole is precisely over the targeted underlying circuitry. It can also be difficult to mill through silicon and to stop at precise depths. Without precisely controllable thinning in lateral and vertical directions, device analysis can be jeopardized.
SUMMARY OF THE INVENTION
The present invention provides methods and apparatuses for detecting the location of a portion of the active circuitry in an integrated circuit, for example, near the circuit side of an integrated circuit die. In this manner, guesswork as to the location of the circuitry while the backside of a die is being removed is eliminated, and the ability to navigate during the milling process is improved. Consequently, failure analysis and debugging of the circuitry associated with a particular integrated circuit is improved. Furthermore, when the position of the circuitry with respect to the milling progress is known or can be determined from the backside removal of the silicon, accessing the circuitry can be accomplished in less time.
In one example embodiment, the present invention provides a method for manufacturing and analyzing the substrate of a semiconductor device to expose selected positions in the substrate. The method includes: forming a three-dimensional pattern in the semiconductor device over a circuit region, the three-dimensional pattern configured and arranged for post-manufacture analysis; and analyzing the circuit region by: removing substrate material from the semiconductor device from a side of the die opposite the circuit region until at least a part of the pattern is detected, and using the detected pattern to determine lateral and depth positions.
In another example embodiment, the present invention involves a method for removing (e.g., by milling) substrate of a semiconductor device and exposing a selected region in the substrate. A three-dimensional pattern is configured and arranged in the semiconductor device over a circuit region, the pattern including a plurality of symbols for recognition using visual means applied to the side of the device opposite the circuit region.
REFERENCES:
patent: 5821549 (1998-10-01), Talbot et al.
patent: 5952247 (1999-09-01), Livengood et al.
Bachand Charles
Bruce Victoria J.
Morrissey Kenneth J.
Stevenson Leslie
Advanced Micro Devices , Inc.
Collins D. M.
Picardat Kevin M.
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