Native composite-field AES encryption/decryption accelerator...

Details Native composite-field AES encryption/decryption accelerator... Native composite-field AES encryption/decryption accelerator...

2007-06-29

2010-12-28

Song, Hosuk (Department: 2435)

Cryptography

Particular algorithmic function encoding

C380S029000

Reexamination Certificate

active

07860240

ABSTRACT:
A system comprises reception of input data of a Galois field GF(2k), mapping of the input data to a composite Galois field GF(2nm), where k=nm, inputting of the mapped input data to an Advanced Encryption Standard round function, performance of two or more iterations of the Advanced Encryption Standard round function in the composite Galois field GF(2nm), reception of output data of a last of the two or more iterations of the Advanced Encryption Standard round function, and mapping of the output data to the Galois field GF(2k).

REFERENCES:
patent: 2008/0253557 (2008-10-01), Dottax et al.
S. Pongyupinpanich, S. Phathumvanh and S. Choomchuay, “A 32 Bits Architecture For An AES System”, International Symposium on communications and Information Technologies, 2004 (ISCIT 2004) Sapporo, Japan, Oct. 26-29, 2004, pp. 70-73.
S. Chantarawong, P. Noo-intara, and S. Choomchuay, “An Architecture for S-Box Computation in the AES”, Proc of Information and Computer Engineering Workshop 2004 (ICEP2004), Prince of Songkla University (Phuket Campus), Jan. 2004, pp. 157-162.

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