Narrow channel MOS devices and method of manufacturing

Details Narrow channel MOS devices and method of manufacturing Narrow channel MOS devices and method of manufacturing

1977-12-21

1980-08-12

James, Andrew J.

357 41, 357 56, 357 91, H01L 2978, H01L 2702, H01L 2906

Patent

active

042175992

ABSTRACT:
Improved, high performance MOS transistors are provided by a method that includes providing an oxygen-impermeable mask on a selected region of a semiconductor substrate, oxidizing the unmasked portion of the surface to provide a thick oxide at least partially recessed in the substrate, which layer includes a smoothly tapered beak that extends between the margin of the mask and the underlying silicon surface, and, after removing the mask, implanting a selected impurity in the substrate beneath the selected region to form a thin impurity layer that terminates at a sloped portion of the substrate formed by the oxidation step.

REFERENCES:
patent: 4029522 (1977-06-01), De La Moneda
patent: 4044452 (1977-08-01), Abbas et al.
patent: 4055444 (1977-10-01), Rao
patent: 4074301 (1978-02-01), Paivinen et al.
patent: 4078947 (1978-03-01), Johnson et al.
patent: 4084175 (1978-04-01), Ouyang
patent: 4091405 (1978-05-01), Ishida
patent: 4108686 (1978-08-01), Jacobus
patent: 4132998 (1979-01-01), Dingwall
IBM Technical Disclosure Bulletin, vol. 10, No. 5, Oct. 1967, by Terman, pp. 653-654.

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