NAPNOP circuit for conserving power in computer systems

Details NAPNOP circuit for conserving power in computer systems NAPNOP circuit for conserving power in computer systems

1993-11-15

1996-08-13

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327227, 327176, 327198, H03K 3033, H03K 3017, H03K 302

Patent

active

055460372

ABSTRACT:
A NAPNOP circuit for decreasing energy consumption of all or a portion of a microprocessor based system which includes a delay circuit for inhibiting or slowing the output of the system clock pulses for a variable length of time equal to a multiple of N clock pulses where N is a positive integer. The NAPNOP circuit has an input element for inputting a STARTNAP signal which begins a nap period during which the system clock pulses are inhibited or slowed, a clock input device for providing a plurality of selectable clock pulses as inputs to the delay circuit for controlling the operation of the computer system, and a gate element for terminating the nap period.

REFERENCES:
patent: 3768026 (1973-10-01), Pezzutti
patent: 5045715 (1991-09-01), Fitch
patent: 5172453 (1992-12-01), Chang et al.
patent: 5313108 (1994-05-01), Lee et al.
patent: 5369311 (1994-11-01), Wang et al.
patent: 5422585 (1995-06-01), Fan Chiangi et al.

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