Nanopore chip with N-type semiconductor

Details Nanopore chip with N-type semiconductor Nanopore chip with N-type semiconductor

2005-01-25

2005-01-25

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S021000, C435S287200

Reexamination Certificate

active

06846702

ABSTRACT:
An apparatus and method for making a nanopore chip exhibiting one of low photosensitivity, low electrical noise, and low electrical drift. The apparatus provides a thin insulating diaphragm containing a nanopore, the diaphragm being supported on a rigid semiconductor frame, the semiconductor frame having N-type doping in those regions which are to be capacitively coupled to an ionic solution. Also disclosed is a method of making the apparatus.

REFERENCES:
patent: 6413792 (2002-07-01), Sauer et al.
patent: 6428959 (2002-08-01), Deamer
patent: 20030013186 (2003-01-01), Martin et al.
patent: WO0181896 (2001-01-01), None
patent: WO0181908 (2001-01-01), None

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