Nanometric structure and corresponding manufacturing method

Details Nanometric structure and corresponding manufacturing method Nanometric structure and corresponding manufacturing method

2005-08-30

2010-11-16

Gurley, Lynne A (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Non-heterojunction superlattice

C977S712000, C977S781000, C257SE25023, C257SE25031, C257SE45001

Reexamination Certificate

active

07834344

ABSTRACT:
A hosting structure of nanometric components is described advantageously comprising: a substrate; n array levels on said substrate, with n≧2, arranged consecutively on growing and parallel planes, each including a plurality of conductive spacers alternated with a plurality of insulating spacers and substantially perpendicular to said substrate, with definition between consecutive conductive spacers of at least a gap, conductive spacers of consecutive array levels lying on distinct and parallel planes, said gaps of different array levels being at least partially aligned along a direction substantially perpendicular to said substrate with definition of a plurality of transversal hosting seats extended along said direction and suitable for hosting at least a nanometric component. A nanometric electronic device is also described comprising such a hosting structure and a method for realizing it.

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