Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Groove formation
Reexamination Certificate
2008-12-31
2010-12-07
Pham, Thanh V (Department: 2894)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Groove formation
C438S039000, C438S696000, C438S699000, C438S702000, C438S703000
Reexamination Certificate
active
07846756
ABSTRACT:
A method of making a device is disclosed including: forming a first hard mask layer over an underlying layer; forming a first imprint resist layer over the underlying layer; forming first features over the first hard mask layer by bringing a first imprint template in contact with the first imprint resist layer; forming a first spacer layer over the first features; etching the first spacer layer to form a first spacer pattern and to expose top of the first features; removing the first features; patterning the first hard mask, using the first spacer pattern as a mask, to form first hard mask features; and etching at least part of the underlying layer using the first hard mask features as a mask.
REFERENCES:
patent: 5915167 (1999-06-01), Leedy
patent: 5977638 (1999-11-01), Rodgers et al.
patent: 6055180 (2000-04-01), Gudesen et al.
patent: 6420231 (2002-07-01), Harari et al.
patent: 6853049 (2005-02-01), Herner
patent: 6946719 (2005-09-01), Petti et al.
patent: 6952030 (2005-10-01), Herner et al.
patent: 7081377 (2006-07-01), Cleeves
patent: 7176064 (2007-02-01), Herner
patent: 7211866 (2007-05-01), Yuan et al
patent: 2004/0245557 (2004-12-01), Seo et al.
patent: 2005/0052915 (2005-03-01), Herner et al.
patent: 2005/0226067 (2005-10-01), Herner et al.
patent: 2006/0250836 (2006-11-01), Herner et al.
patent: 2006/0250837 (2006-11-01), Herner et al.
patent: 2006/0273298 (2006-12-01), Petti
patent: 2007/0072360 (2007-03-01), Kumar et al.
patent: 2007/0114509 (2007-05-01), Herner
patent: 2007/0164309 (2007-07-01), Kumar et al.
patent: 2008/0013364 (2008-01-01), Kumar et al.
patent: 2009/0239382 (2009-09-01), Zhu
U.S. Appl. No. 09/560,626, filed Apr. 28, 2000, Knall.
U.S. Appl. No. 11/864,205, filed Sep. 28, 2007, Yung-Tin Chen et al.
U.S. Appl. No. 11/864,532, filed Sep. 28, 2007, Maxwell.
U.S. Appl. No. 12/000,758, filed Dec. 17, 2007, Petti et al.
U.S. Appl. No. 12/007,780, filed Jan. 15, 2008, Herner et al.
U.S. Appl. No. 12/007,781, filed Jan. 15, 2008, Dunton et al.
U.S. Appl. No. 12/216,107, filed Jun. 30, 2008, Chan.
U.S. Appl. No. 12/149,151, filed Apr. 28, 2008, Chen et al.
U.S. Appl. No. 12/222,293, filed Aug. 6, 2008, Chan.
U.S. Appl. No. 12/289,396, filed Oct. 27, 2008, Chen et al.
Kim, Ryoung H. et al., “Double Exposure Using 193 nm Negative Tone Photoresist”, Optical Microlithography XX, Proc of SPIE, vol. 6520, 65202M, 2007, 8 pgs.
Nakamura, Hiroko et al., “Contact Hole Formation by Multiple Exposure Technique in Ultra-low k1Lithography”, Optical Microlithography XVII, Proceedings of SPIE, vol. 5377, Feb. 24-27, 2004, pp. 255-263.
Nakamura, Hiroko et al., “Low k1Contact Hole Formation by Double Line and Space Formation Method with Contact Hole Mask and Dipole Illumination”, The Japan Society of Applied Physics, vol. 45, No. 6B, 2000, pp. 5409-5417.
U.S. Appl. No. 12/318,609, filed Dec. 31, 2008, Chen et al.
Chen Yung-Tin
Maxwell Steven
Wang Chun-Ming
Yen Bing K.
Pham Thanh V
SanDisk 3D LLC
The Marbury Law Group PLLC
Tran Tony
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