Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2002-12-17
2004-03-09
Wille, Douglas (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S015000
Reexamination Certificate
active
06703639
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a heterostructure manufacturing method and device and, more particularly, to the nanofabrication of heterostructure devices.
2. Description of the Prior Art
Rapidly developing nanofabrication technologies such as electron-beam (e-beam) and atomic-force-microscope (AFM) lithography and a variety of growth/synthesis techniques have enabled a number of material systems to exhibit mesoscopic phenomena. Some of these systems include metallic wires/rings, carbon nanotubes, and GaAs/AlGaAs heterostructures. Among these, the GaAs/AlGaAs system is the most intensively studied due to the long mean free path (l
e
) of two-dimensional (2D) electrons in heterojunctions. As a result, it is possible with current technology to fabricate ballistic one-dimensional (1D) wires, where W<L<l
e
and Wand L are the lateral confinement dimension of the device, i.e., width and length, respectively. The lateral confinement can be accomplished by a number of methods, e.g., mesa-etch or split-gate approaches. However, due to mid-gap pinning of the surface Fermi level (E
f
s
) in the GaAs/AlGaAs system, electrons are completely depleted in heterojunctions whose metallurgical width (Wm) is narrower than 0.5 &mgr;m or so. Recently, a number of variations on nanofabrication, e.g., AFM anodization and front-gate induction, have been attempted to further reduce device dimensions.
The 2D electrons in InAs quantum wells (QW's) are also known to have a long mean free path. In addition, InAs has a number of properties that are advantageous for nanofabrication and for studying low-dimensional physics. First, the surface Fermi level pinning position in InAs, E
f
s
(InAs), is above the conduction band. This property makes it possible to fabricate isolated conducting wires with widths in nanometers, which suggests the possibility of fabricating a complex circuit with compact dimensions. Second, a small electron effective mass (0.023 m
0
) results in a large quantization energy, which is favorable for the observation of low-dimensional phenomena at higher temperatures. Finally, the relatively large Lande g-factor (g
0
=−15) is essential for studying spin related physics, e.g., Berry's phase resulting from the Rashba effect.
Although nanotechnology is a rapidly evolving field, current InAs nanofabrication is limited. For example, nanotechnology fabrication has been used to form InAs conducting wires and rings as well as double-barrier-tunneling dots with a minimum dimension of 30 nm using e-beam lithography and reactive-ion etching (RIE). However, these InAs devices have been limited in applicability for particular applications since the electron beam free path decreases as the wire width is reduced due to damage on the side wall and the top surface during dry etching and O
2
ashing. Further, using prior nanofabrication techniques, ultra smallness is obtained at the expense of material quality, which is a drawback for practical applications.
Previous attempts of overcoming the aforementioned limitations of these manufacturing methods and resulting InAs devices, namely limitations due to side wall and top surface damage, includes the use of chemical etching which typically results in minimal damage. Using conventional chemical etching techniques and etchant solutions, a 20 nm depth wet etch can provide isolation of InAs wires. However, the marginal control of side wall roughness characteristic of this method, limits application of the method for deep submicron device fabrication. Generally speaking, the deeper the etched pattern, the rougher the side wall will be. As a result, chemical etching is rarely applied to nanofabrication. Moreover, lateral isolation by the physical isolation of an InAs quantum well may not be the ideal choice since the conducting electrons will be in close proximity to the surface states and may suffer from excess scattering.
SUMMARY OF THE INVENTION
The present invention concerns a heterostructure device and manufacturing method that provides for nanofabrication of heterostructure devices including quantum wells. These heterostructure devices may be used for conducting wires commonly referred to as quantum wires. The device is formed from a suitable substrate having a quantum well formed therein, barrier layers located above and below the quantum well, and a cap layer formed on the top barrier layer, in which the cap layer is a p-doped material which provides the requisite depletion of 2D electrons from the quantum well.
Chemical etching is conducted using an appropriate etchant to form the desired structure depending on the substrate to be etched. Appropriate etchants include (1) acetic acid and hydrogen peroxide to etch InAs; and (2) hydrogen fluoride, hydrogen peroxide and lactic acid; and (3) AZ400K to etch AlSb, GaSb and their alloys.
According to one aspect of the present invention, a heterostructure comprises a buffer layer and a bottom barrier layer formed on the buffer layer. A quantum well layer is formed on the bottom barrier layer. A top barrier layer is then formed on the quantum well layer. A p-doped cap layer is formed on the top barrier layer. A portion of the cap layer is etched to form conducting electrons in the quantum well layer below the etched portion of the cap layer.
According to another aspect of the present invention, a heterostructure comprises an Al
x
Ga
1−x
Sb buffer layer and an Al
x
Ga
1−x
Sb bottom barrier layer formed on the buffer layer. An InAs quantum well layer is formed on the bottom barrier layer. An Al
x
Ga
1−x
Sb top barrier layer is formed on the quantum well layer and a cap comprising a first InAs cap layer, an Al
x
Ga
1−x
Sb cap layer, and a second InAs cap layer is formed on the top barrier layer. The second InAs cap layer is etched to form conducting electrons in the quantum well layer below the etched portion of the second InAs cap layer.
According to another aspect of the present invention, a method of fabricating a heterostructure device includes providing a buffer layer and growing a bottom barrier layer on the buffer layer. A quantum well layer is grown on the bottom barrier layer and a top barrier layer is grown on the quantum well layer. A p-doped cap layer is formed on the top barrier layer. A portion of the cap layer is etched to form conducting electrons in the quantum well layer below the etched portion of the cap layer
According to yet another aspect of the present invention, an etching method is provided which includes providing a heterostructure and providing an etchant solution comprising acetic acid, hydrogen peroxide, and water. The etchant solution in contacted to the heterostructure to etch the heterostructure.
According to further aspect of the present invention, an etching method is provided which includes providing a heterostructure and providing an etchant solution comprising hydrofluoric acid, hydrogen peroxide, and lactic acid. The etchant solution in contacted to the heterostructure to etch the heterostructure.
According to another aspect of the present invention, an etching method is provided which includes providing an Al
x
Ga
1−x
Sb heterostructure and providing an etchant solution comprising AZ400K and water. The etchant solution in contacted to the heterostructure to etch the heterostructure.
Further features and advantages of the present invention will be set forth in, or apparent from, the detailed description of preferred embodiments thereof which follows.
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Yang Chia-Hung
Yang Ming-Jey
Grnkemeyer Joseph T.
Karasek John J.
The United States of America as represented by the Secretary of
Wille Douglas
LandOfFree
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