Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-12-19
2003-05-27
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185010, C365S189011
Reexamination Certificate
active
06570786
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a NAND-type memory array and method of reading, programming and erasing the same, and more particularly to, a NAND-type memory array and method of reading, programming and erasing the same capable of preventing lowering in the read speed by separating well and bit line.
2. Description of the Prior Art
Generally, in a NAND-type memory array using a deep trench isolation (DTI) scheme, all the well bias is applied via bit line upon reading, programming and erasure since it employs an independent well.
FIGS. 1A and 1B
are cross-sectional views of a conventional NAND-type memory array, wherein
FIG. 1A
is a cross-sectional view of the memory array taken along in a word line direction of the array and
FIG. 1B
is a cross-sectional view of the memory array taken along in a bit line direction of the array.
A construction of the conventional NAND-type memory array will be described by reference to
FIGS. 1A and 1B
.
Referring now to
FIG. 1A
, a triple N well
12
is formed on a P type substrate
11
and triple P well
13
are then formed to be included in the triple N well
12
. The triple P well
13
are divided by a plurality of numbers, by means of a plurality of dip trench device isolation films
14
. Floating gates
17
are formed on the triple P well
13
, respectively. Word lines
20
are overlapped with the floating gates
17
.
Referring now to
FIG. 1B
, first~eleventh N
+
junctions
15
a
~
15
k
and a P
+
junction
16
are formed within the triple P well
13
in an isolated fashion. First~sixth floating gates
17
a
~
17
f
are formed on the triple P well
13
in an isolated fashion. Source nodes
19
are connected to the second N
+
junction
15
b
. Each of first~second source select lines
18
a
and
18
b
is formed at both sides of the second N
+
junction
15
b
. A bit line
23
is connected to a P
+
junction
16
, and seventh and eighth N
+
junctions
15
g
and
15
h
formed at both sides of the P
+
junction
16
, respectively.
A first drain select line
22
a
is formed at one side of the seventh N
+
junction
15
g
and a second drain select line
22
b
is formed at one side of the eighth N
+
junction
15
h
. Between a second source select line
18
b
and the first drain select line
22
a
, a first pass gate
20
a
is overlapped with the first floating gate
17
a
, a first cell gate
21
a
is overlapped with the second floating gate
17
b
, a second pass gate
20
b
is overlapped with the third floating gate
17
c
. At this time, the first cell gate
21
b
is located between the first pass gate
20
a
and the second pass gate
20
b
. Similarly in the second drain select line
22
b
, a third pass gate
20
c
is overlapped with the fourth floating gate
17
d
, a second cell gate
21
b
is overlapped with the fifth floating gate
17
e
and a fourth pass gate
20
d
is overlapped with the sixth floating gate
17
f.
In the above, each of the source node
19
, the source select lines
18
a
and
18
b
, the drain select lines
22
a
and
22
b
, the pass gates
20
a
~
20
d
, and the cell gates
21
a
and
21
b
is formed in the triple P well
13
in a crossing direction. The bit line
23
is formed in a direction of the triple P well
13
.
It is known that the NAND-type memory array is based on the above construction and this basic construction is constantly arranged.
An operation of reading, programming and erasing the conventional NAND-type memory array will be described by reference to
FIG. 2
showing a node bias condition of the NAND-type memory array.
First, the read operation includes applying a voltage of 0~1V to the bit line
23
, applying a voltage of 0V to the triple P well
13
, applying a voltage of 3V to the source node
19
, applying a voltage of 5V to the drain select line
22
, applying a voltage of 5V to the source select line
18
, applying a voltage of 3V to the cell gate
21
and applying a voltage of 3V to the triple N well
12
.
The program operation includes applying a voltage of −9V to the bit line
23
, applying a voltage of −9V to the triple P well
13
, applying a voltage of 0V to the source node
19
, applying a voltage of 0V to the drain select line
22
, applying a voltage of −9V to the source select line
18
, applying a voltage of 9V to the cell gate
21
and applying a voltage of 0V to the triple N well
12
.
The erase operation includes applying a voltage of 9V to the bit line
23
, applying a voltage of 9V to the triple P well
13
, making the source node
19
floated, making the drain select lines
22
floated, making the source select lines
18
floated, applying a voltage of −9V the cell gate
21
and applying a voltage of 9V to the triple N well
12
.
In the above conventional NAND-type memory array, as the triple P well
13
is independently driven by the dip trench device isolation film
14
in structure, it is required that all the well bias be applied via the bit line
23
upon reading, programming and erasure operation.
It is inevitable that the bias is applied to the well in programming and erasure operations using this method. In a reading operation, however, there is a problem that the read speed is lowered due to a well loading if this method is used. In other words, if a voltage of 3V is applied to the source node
19
and a voltage of 3V is applied to the cell gate
21
upon a reading operation, a bias passing the cell is applied to the bit line
23
, which charges the well via the P
+
junction
16
. As such, as the loading of the triple P well
13
is generated upon a reading operation, delay in the speed is caused.
SUMMARY OF THE INVENTION
The present invention is contrived to solve this problem and an object of the present invention is to provide a NAND-type memory array and method of reading, programming and erasing the same capable of preventing lowering in the speed upon a reading operation, by separating well and bit line.
In order to accomplish the above object, a NAND-type memory array according to the present invention is characterized in that it comprises P type substrate in which a triple P well is formed; first~eighth N
+
junctions, a P
+
junction and ninth fourteenth N
+
junctions, which are sequentially formed within the triple P well; first~sixth floating gates formed on the triple P well; source node connected to the second N
+
junction; first and second source select lines each formed at both sides of the second N
+
junction; bit line each connected to the seventh and eleventh N
+
junctions; first drain select line formed at one side of the N
+
junction and second drain select line formed at one side of the eleventh N
+
junction; first pass gate, first cell gate and second pass gate each formed between the second source select line and the first drain select line; third pass gate, second cell gate and fourth pass gate each formed on the triple P well on the second drain select line’ side; interconnection line connecting the eighth N
+
junction, the P
+
junction and the ninth N
+
junction, respectively; program well select gate formed between the seventh N
+
junction and the eighth N
+
junction; P well node connected to the tenth N
+
junction between the ninth N
+
junction and the eleventh N
+
junction; and triple P well select gate formed between the ninth N
+
junction and the tenth N
+
junction, wherein the elements being a basic construction and this basic construction is constantly arranged.
In the above, the triple P well is formed within the triple N well. The pass gates and the cell gates are overlapped with the floating gates, respectively. The cell gates have the pass gates located at its both side, respectively.
The source nodes, the source select lines, the drain select lines, the pass gates and the cell gates are each formed in a direction crossing with the triple P well. The bit line are formed in a direction of the trip
Hynix Semiconductorr Inc.
Morgan & Lewis & Bockius, LLP
Nelms David
Yoha Connie C.
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