Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2011-01-11
2011-01-11
Hur, J. H. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185020, C365S185030, C365S185080, C365S185170, C365S185240, C365S185250
Reexamination Certificate
active
07869276
ABSTRACT:
A memory includes many memory regions. The memory regions have multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The first bit line is coupled to a first column of the multi-level cells. The second bit line is coupled to a second column of the multi-level cells. The data buffer is coupled to the first bit line and the second bit line and for storing data to be programmed into the multi-level cells. The protecting unit is coupled to the first bit line, the second bit line and the data buffer and is for preventing a programming error from occurring.
REFERENCES:
patent: 2002/0126531 (2002-09-01), Hosono et al.
patent: 2003/0016562 (2003-01-01), Im
patent: 2010/0027339 (2010-02-01), Ho et al.
Chang Chin-Hung
Chang Kuen-Long
Ho Wen-Chiao
Hung Chun-Hsiung
Hur J. H.
Macronix International Co. Ltd.
Thomas Kayden Horstemeyer & Risley
LandOfFree
Nand type memory and programming method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nand type memory and programming method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nand type memory and programming method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2727668