Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2005-08-16
2005-08-16
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185170
Reexamination Certificate
active
06930921
ABSTRACT:
A nonvolatile semiconductor memory device includes a NAND memory cell array, booster circuit, row decoder, bit line control circuit and column decoder. In the device, the magnitude of intermediate voltage applied to the control gates of memory transistors from the booster circuit via the row decoder is changed according to the position of a selected control gate line when data is sequentially programmed into the memory transistors in the memory cell array. Alternatively, a plurality of different intermediate voltages are applied when data is simultaneously programmed into memory transistors connected to the selected control gate line.
REFERENCES:
patent: 5745413 (1998-04-01), Iwahashi
patent: 5969990 (1999-10-01), Arase
patent: 6064611 (2000-05-01), Tanaka et al.
patent: 6363010 (2002-03-01), Tanaka et al.
patent: 2002/0126532 (2002-09-01), Matsunaga et al.
patent: 08-279297 (1996-10-01), None
patent: 10-283788 (1998-10-01), None
patent: 2002-260390 (2002-09-01), None
Kang-Deog Shu, et al. “A 3.3 V 32 Mb Nand Flash Memeory With Incremental Step Pulse Programming Sheme” IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995, pp. 1149-1155.
Arai Fumitaka
Matsunaga Yasuhiko
Yaegashi Toshitake
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