NAND type flash EEPROM in which sequential programming...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185170, C365S185110

Reexamination Certificate

active

06859395

ABSTRACT:
A nonvolatile semiconductor memory device includes a NAND memory cell array, booster circuit, row decoder, bit line control circuit and column decoder. In the device, the magnitude of intermediate voltage applied to the control gates of memory transistors from the booster circuit via the row decoder is changed according to the position of a selected control gate line when data is sequentially programmed into the memory transistors in the memory cell array. Alternatively, a plurality of different intermediate voltages are applied when data is simultaneously programmed into memory transistors connected to the selected control gate line.

REFERENCES:
patent: 5969990 (1999-10-01), Arase
patent: 6363010 (2002-03-01), Tanaka et al.
patent: 20020126532 (2002-09-01), Matsunaga et al.
patent: 08279297 (1996-10-01), None
patent: 10283788 (1998-10-01), None
patent: 2002260390 (2002-09-01), None
Kang-Deog Shu, et al. “A 3.3 V 32 Mb NAND Flash Memory With Incremental Step Pulse Programming Scheme” IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995, pp. 1149-1155.

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