NAND-type EEPROM having bit lines and source lines commonly coup

Details NAND-type EEPROM having bit lines and source lines commonly coup NAND-type EEPROM having bit lines and source lines commonly coup

1994-03-18

2000-11-21

Tran, Andrew Q.

Static information storage and retrieval

Floating gate

Particular connection

36518502, 365103, 365104, 257314, 257315, G11C 1604

Patent

active

061512494

ABSTRACT:
In an EEPROM including a plurality of NAND memory cells each constituted by connecting memory cells each having a floating gate and a control gate in series with each other, first selection transistors respectively coupled between the same bit line and terminals, on one side, of each pair constituted by two NAND memory cells of the plurality of memory cells, and second selection transistors respectively coupled between terminals on the other side and source lines (SL), the first or second selection transistors are constituted by an enhancement transistor and a depletion transistor which are coupled in series with each other, and the arrangements of the depletion transistor and enhancement transistor of the first selection transistors are reversed to those of the second selection transistors in the same NAND memory cells.

REFERENCES:
patent: 4962481 (1990-10-01), Choi et al.
patent: 4980861 (1990-12-01), Herdt et al.
patent: 5043942 (1991-08-01), Iwata et al.
patent: 5050125 (1991-09-01), Momodomi et al.
patent: 5111428 (1992-05-01), Liang et al.
patent: 5253206 (1993-10-01), Tanaka et al.
"Densely arrayed EEPROM having low-voltage tunnel write", E. Adler, IBM TDB, vol. 27, No. 6, Nov. 1984, pp. 3302-3307.

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