NAND-type dynamic RAM having temporary storage register and sens

Static information storage and retrieval – Addressing – Plural blocks or banks

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36518905, G11C 800

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active

058927247

ABSTRACT:
A sense amplifier is connected between memory cell arrays, a re-writing register is arranged adjacent to the sense amplifier, first transfer gates are disposed between the sense amplifier and the memory cell arrays, second transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.

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1993 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, vol. 36, pp. 46-47, Takehiro Hasegawa, et al., "An Experimental DRAM with a NAND-Structured Cell".

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