NAND-structured flash memory

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S200000, C365S185170

Reexamination Certificate

active

11057203

ABSTRACT:
A NAND-structured flash memory comprises a memory cell array wherein plural memory strings are arranged in matrix form, each of the memory cell strings including plural nonvolatile memory cells, the first conducting paths of the memory cells being connected in series, at least one of the memory cells having a function other than an external data storing function, plural first selection transistors having second conducting paths, and one end of the second conducting paths being connected to one end of the series of the first conducting paths, respectively, plural bit lines connected to the other end of the second conducting paths, plural second selection transistors having third conducting paths, and one end of the third conducting paths being connected to one end of the series of the first conducting paths, respectively, and a source line connected to the other end of the third conducting paths.

REFERENCES:
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6061270 (2000-05-01), Choi
patent: 7079437 (2006-07-01), Hazama et al.
patent: 2005/0056869 (2005-03-01), Ichige et al.
patent: 2005/0174852 (2005-08-01), Hemink
patent: 10-199280 (1998-07-01), None
patent: 2002-237194 (2002-08-01), None

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