NAND string wordline delay reduction

Details NAND string wordline delay reduction NAND string wordline delay reduction

2006-06-20

2006-06-20

Mai, Son (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185020, C365S185180

Reexamination Certificate

active

07064981

ABSTRACT:
An improved NAND Flash memory and word line selection method has been described, that takes advantage of the asymmetric nature of the word line to word line capacitive coupling to reduce word line selection delay by driving the adjacent word lines to a higher initial voltage and then reducing it to the final target voltage. As the capacitive coupling in between the NAND word lines is a larger effect when the voltages are being lowered, this has the effect of damping out the voltage initially induced in the lower voltage word line by the rising voltages on the adjacent word lines, reducing the overall selection time.

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patent: 2005/0157578 (2005-07-01), Noguchi et al.
patent: 2005/0185468 (2005-08-01), Hosono et al.

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