NAND or NOR compound semiconductor memory

Details NAND or NOR compound semiconductor memory NAND or NOR compound semiconductor memory

1997-10-08

2000-02-15

Guay, John

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

257316, 36518517, H01L 29788, H01L 29772

Patent

active

060256125

ABSTRACT:
A compound semiconductor memory has a second semiconductor layer (undoped AlGaAs hetero-barrier layer), a third semiconductor layer (n type InGaAs layer), a fourth semiconductor layer (undoped AlGaAs layer) and a gate electrode of WSi selectively deposited in order on an n type first semiconductor layer (n type GaAs channel layer). A drain electrode and a source electrode, which are electrically connected to the first semiconductor layer are formed on those areas of the first semiconductor layer where the second semiconductor layer or the like is not formed. At this time, the potential barrier of a floating gate (third semiconductor layer) on the gate electrode side is set higher than the potential barrier of the floating gate (first semiconductor layer) on the channel layer side.

REFERENCES:
patent: 5147817 (1992-09-01), Frazier et al.
patent: 5432356 (1995-07-01), Imamura
patent: 5589699 (1996-12-01), Araki
patent: 5814855 (1998-09-01), Arase et al.

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