NAND memory device and programming methods

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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Details

C365S185120, C365S185170, C365S185220, C365S185290, C365S185330

Reexamination Certificate

active

07952924

ABSTRACT:
A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines of an array row are concurrently programmed as a common page. Floating gate coupling during programming can therefore be reduced. Multiple verify operations are performed on separate bit lines of the page. Bit line coupling can therefore be reduced.

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