Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-04-04
2006-04-04
Mai, Son (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185020, C365S185170, C365S185190
Reexamination Certificate
active
07023739
ABSTRACT:
An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
REFERENCES:
patent: 4142176 (1979-02-01), Dozier
patent: 4543594 (1985-09-01), Mohsen et al.
patent: 4602354 (1986-07-01), Craycraft et al.
patent: 4646266 (1987-02-01), Ovshinsky et al.
patent: 4868616 (1989-09-01), Johnson et al.
patent: 5197027 (1993-03-01), Challa
patent: 5299166 (1994-03-01), Suh et al.
patent: 5301144 (1994-04-01), Kohno
patent: 5412493 (1995-05-01), Kunii et al.
patent: 5429968 (1995-07-01), Koyama
patent: 5473563 (1995-12-01), Suh et al.
patent: 5514907 (1996-05-01), Moshayedi
patent: 5568421 (1996-10-01), Aritome
patent: 5621683 (1997-04-01), Young
patent: 5644533 (1997-07-01), Lancaster et al.
patent: 5703382 (1997-12-01), Hack et al.
patent: 5715194 (1998-02-01), Hu
patent: 5751012 (1998-05-01), Wolstenholme et al.
patent: RE35838 (1998-07-01), Momodomi et al.
patent: 5812457 (1998-09-01), Arase
patent: 5814853 (1998-09-01), Chen
patent: 5835396 (1998-11-01), Zhang
patent: 5898615 (1999-04-01), Chida
patent: 5923587 (1999-07-01), Choi
patent: 5926415 (1999-07-01), Shin
patent: 5940321 (1999-08-01), Takeuchi et al.
patent: 5978265 (1999-11-01), Kirisawa et al.
patent: 5991202 (1999-11-01), Derhacobian et al.
patent: 6005270 (1999-12-01), Noguchi
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6049494 (2000-04-01), Sakui et al.
patent: 6055180 (2000-04-01), Gudesen et al.
patent: 6061270 (2000-05-01), Choi
patent: 6107658 (2000-08-01), Itoh et al.
patent: 6108238 (2000-08-01), Nakamura et al.
patent: 6115287 (2000-09-01), Shimizu et al.
patent: 6151249 (2000-11-01), Shirota et al.
patent: 6163048 (2000-12-01), Hirose et al.
patent: 6185122 (2001-02-01), Johnson et al.
patent: 6188611 (2001-02-01), Endoh et al.
patent: 6291836 (2001-09-01), Kramer et al.
patent: 6295227 (2001-09-01), Sakui et al.
patent: 6307807 (2001-10-01), Sakui et al.
patent: 6326269 (2001-12-01), Jeng et al.
patent: 6373746 (2002-04-01), Takeuchi et al.
patent: 6380636 (2002-04-01), Tatsukawa et al.
patent: 6420215 (2002-07-01), Knall et al.
patent: 6434053 (2002-08-01), Fujiwara
patent: 6445613 (2002-09-01), Nagai
patent: 6456528 (2002-09-01), Chen
patent: 6469933 (2002-10-01), Choi et al.
patent: 6473328 (2002-10-01), Mercaldi
patent: 6477077 (2002-11-01), Okazawa
patent: 6490194 (2002-12-01), Hoenigschmid
patent: 6498747 (2002-12-01), Gogl et al.
patent: 6512694 (2003-01-01), Herdt
patent: 6512703 (2003-01-01), Sakui et al.
patent: 6515888 (2003-02-01), Johnson et al.
patent: 6522583 (2003-02-01), Kanda et al.
patent: 6545898 (2003-04-01), Scheuerlein
patent: 6567312 (2003-05-01), Torii et al.
patent: 6597609 (2003-07-01), Chevallier
patent: 6611453 (2003-08-01), Ning
patent: 6614688 (2003-09-01), Jeong et al.
patent: 6618292 (2003-09-01), Sakui
patent: 6621743 (2003-09-01), Ogane
patent: 6671204 (2003-12-01), Im
patent: 6822903 (2004-11-01), Scheuerlein et al.
patent: 6849905 (2005-02-01), Ilkbahar et al.
patent: 6853587 (2005-02-01), Forbes
patent: 6856572 (2005-02-01), Scheuerlein et al.
patent: 6859395 (2005-02-01), Matsunaga et al.
patent: 6859410 (2005-02-01), Scheuerlein et al.
patent: 2001/0055838 (2001-12-01), Walker et al.
patent: 2002/0021587 (2002-02-01), Sakui et al.
patent: 2002/0028541 (2002-03-01), Lee et al.
patent: 2003/0155582 (2003-08-01), Mahajani et al.
patent: 2004/0124415 (2004-07-01), Walker et al.
patent: 2004/0124466 (2004-07-01), Walker et al.
patent: 2004/0125629 (2004-07-01), Scheuerlein et al.
patent: 2004/0145024 (2004-07-01), Chen et al.
patent: 2005/0111260 (2005-05-01), Nazarian
patent: 0 528 367 (1993-02-01), None
patent: 0 575 051 (1993-12-01), None
patent: 62-142363 (1987-06-01), None
patent: 62-155568 (1987-07-01), None
patent: 1998-10149688 (1998-06-01), None
patent: 2001-358237 (2001-12-01), None
patent: 2002-280467 (2002-09-01), None
Durisety, Chandra Sekhar Acharyulu, “Analysis and Characterization of Single-Poly Floating Gate Devices in 0.35um PDSOI Process”, A Thesis Presented for the Master of Science Degree, The University of Tennessee, Knoxville, Dec. 2002, pp. i-viii and 1-80.
Evans, Robert J., et al., “Energy Consumption Modeling and Optimization for SRAM's,” IEEE Journal of Solid-State Circuits, vol. 30, No. 5, May 1995, pp. 571-579.
Jung, Tae-Sung, et al., “A 117-mm23.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications,” IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1575-1583.
Kawagoe, Hiroto, et al., “Minimum Size ROM Structure Compatible with Silicon-Gate E/D MOS LSI,” IEEE Journal of Solid-State Circuits, vol. SC-11, No. 3, Jun. 1976, pp. 360-364.
Kim, Kyu-Hyoun, et al., “An 8-Bit-Resolution, 360-μs Write Time Nonvolatile Analog Memory Based on Differentially Balanced Constant-Tunneling-Current Scheme (DBCS),” IEEE Journal of Solid-State Circuits, vol. 33, No. 11, Nov. 1998, pp. 1758-1762.
Kim, Byungcheul, et al., “A Scaled SONOS Single-Transistor Memory Cell for a High-Density NOR Structure with Common Source Lines,” Journal of the Korean Physical Society, vol. 41, No. 6, Dec. 2002, pp. 945-948.
Kim, Byungcheul, et al., “Single Power Supply Operated and Highly Reliable SONOS EEPROMs,” Journal of the Korean Physical Society, vol. 40, No. 4, Apr. 2002, pp. 642-644.
Kitano, Yoshitaka, et al., “A 4-Mbit Full-Wafer ROM,” IEEE Journal of Solid-State Circuits, vol. SC-15, No. 4, Aug. 1980, pp. 686-693.
Lee, Yong Kyu, et al., “Multilevel Vertical-Channel SONOS Nonvolatile Memory on SOI,” IEEE Electron Device Letters, vol. 23, No. 11, Nov. 2002, pp. 664-666.
Lin, Horng-Chih, et al., “Ambipolar Schottky-Barrier TFTs,” IEEE Transactions on Electron Devices, vol. 49, No. 2, Feb. 2002, pp. 264-270.
Najeeb-Ud-Din et al., “Analysis of Floating Body Effects in Thin Film Conventional and Single Pocket SOI MOSFETs Using the GIDL Current Technique”, IEEE Electron Device Letters, vol. 23, No. 4, Apr. 2002, pp. 209-211.
Nishihara, Toshiyuki, et al., “A Quasi-Matrix Ferroelectric Memory for Future Silicon Storage,” IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1479-1484.
Park, Ki-Tae, “Recent Non-Volatile Memory Device & Circuit Technology,” Halo LSI Inc, (date unknown), 35 pages.
Roizin, Yakov, et al., “Plasma-Induced Charging in Two Bit per Cell SONOS Memories,” Tower Semiconductor Ltd., Migdal HaEmek 23105, Israel, (date unknown), 4 pages.
Shin, Jongshin, et al., “A New Charge Pump Without Degradation in Threshold Voltage Due to Body Effect,” IEEE Journal of Solid-State Circuits, vol. 35, No. 8, Aug. 2000, pp. 1227-1230.
Sturm, J. C., et al., “Leakage Current Modeling of Series-Connected Thin Film Transistors,” IEEE Transactions on Electron Devices, vol. 42, No. 8, Aug. 1995, pp. 1561-1563.
Sugibayashi, Tadahiko, et al., “A 30-ns 256-Mb DRAM with a Multidivided Array Structure,” IEEE Journal of Solid-State Circuits, vol. 28, No. 11, Nov. 1993, pp. 1092-1098.
Suh, Kang-Deog, et al., “3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” IEEE Journal of Solid-State Circuits, vol. 30, No. 11 Nov. 1995, pp. 1149-1156.
Takeuchi, Ken, et al., “A Negative
Chen En-Hsing
Fasoli Luca G.
Ilkbahar Alper
Nallamothu Sucheta
Scheuerlein Roy E.
Mai Son
Matrix Semiconductor Inc.
Zagorin O'Brien Graham LLP
LandOfFree
NAND memory array incorporating multiple write pulse... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with NAND memory array incorporating multiple write pulse..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and NAND memory array incorporating multiple write pulse... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3604820