Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1989-10-19
1991-10-22
Miller, Stanley D.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307449, 307443, 307452, 307453, H03K 19017, H03K 19094, H03K 1920, H03K 17687
Patent
active
050598252
ABSTRACT:
A NAND gate circuit which can be used for a decoder circuit, includes a high potential voltage source (V.sub.cc), an output terminal (V.sub.OUT), and a load element (T.sub.1) connected between the high potential electric voltage source (V.sub.cc) and the output terminal (V.sub.OUT). A driving circuit is serially connected with the output terminal (V.sub.OUT), and a low potential voltage source (V.sub.ss), and has a plurality of driving transistors (T.sub.2, T.sub.3) which are serially arranged. An input signal is applied to each gate. At least one transistor, constituting the driving circuit, has a driving performance different from the other transistors of the driving circuit. An ideal NAND gate circuit can be provided in which erroneous operation due to noise can be effectively prevented by setting the input threshold voltage to a constant voltage no matter what the combination of the input signals.
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Patent abstracts of Japan, vol. 6, No. 144 (E-122)[1022], Aug. 3, 1982 & JP-Aj-57 67 333 (Matsushita Denki Sangyo K.K.), Apr. 23, 1982.
Patent abstracts of Japan, vol. 2, No. 51, Apr. 12, 1978, p. 965 E 78, & JP-A-53 15 055 (Tokyo Shibaura Denki K. K.), 02-10-1978.
IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, Oct. 1984, pp. 657-663, IEEE, New York, U.S., S. Tanaka et al., "A Subnanosecond 8K-Gate CMOS/SOS Gate Array".
Bertelson David R.
Fujitsu Limited
Miller Stanley D.
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