NAND flash memory device capable of improving read speed

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S189050, C365S200000

Reexamination Certificate

active

11285273

ABSTRACT:
A NAND flash memory device which includes a first page buffer circuit reading main data bits from the main field during a read operation, a second page buffer circuit reading redundant data bits from the redundancy field during the read operation, a first column gate circuit configured to select a part of the read main data bits and a part of the read redundant data bits in response to first column selection signals at the same time, and a second column gate circuit configured to select a part of the selected main data bits in response to second column selection signals.

REFERENCES:
patent: 5289413 (1994-02-01), Tsuchida et al.
patent: 6462998 (2002-10-01), Proebsting
patent: 1993 05182491 (1993-07-01), None
patent: 1998 055765 (1998-09-01), None
patent: 1999 0079926 (1999-11-01), None
patent: 2002 0094356 (2002-12-01), None
English Abstract.

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