NAND flash memory cell array with adaptive memory state...

Details NAND flash memory cell array with adaptive memory state... NAND flash memory cell array with adaptive memory state...

2006-12-29

2009-02-10

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185180, C365S185230

Reexamination Certificate

active

07489548

ABSTRACT:
A NAND type flash memory is organized into NAND strings with each being a chain of memory cells in series and connected via select transistors on both ends of the string to either a bit line or a source line. The memory cells adjacent both ends of a NAND string are particularly susceptible to errors due to program disturb. An adaptive memory-state partitioning scheme is employed to overcome the errors, in which each memory cells are generally partitioned to store multiple bits of data, except for the ones adjacent both ends where relatively less bits are stored. In this way, the storage of relatively less bits in the memory cells adjacent both ends of a NAND string affords sufficient margin to overcome the errors. For example, in a memory designed to store 2-bit data, the cells adjacent both ends of a NAND string would each be configured to store one bit of the 2-bit data.

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