NAND flash memory array with cut-off gate line and methods...

Details NAND flash memory array with cut-off gate line and methods... NAND flash memory array with cut-off gate line and methods...

2011-08-09

2011-08-09

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185330, C365S226000

Reexamination Certificate

active

07995390

ABSTRACT:
A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a control gate in order to operate two cells having vertical channels independently with one control gate (i.e., a shared word line). The memory cell area is reduced considerably compared to the conventional vertical channel structure, and is better for high integration. A shared cut-off gate turn off is made during a programming operation and prevents programming the opposite cell by a self-boosting effect. It is possible to shield electrically with a shared word line (a control gate) during a reading operation, and minimizes the effect of storage condition of the opposite cell. Also, the NAND flash memory array can be fabricated by using the conventional CMOS process.

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