Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2008-07-15
2008-07-15
Elms, Richard T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185060, C365S185120, C365S238500, C365S230080
Reexamination Certificate
active
11833051
ABSTRACT:
A semiconductor integrated circuit device includes even-numbered bit lines, odd-numbered bit lines, cell source lines, first memory elements electrically connected between the even-numbered bit lines and the cell source lines, and second memory elements electrically connected between the odd-numbered bit lines and the cell source lines and belonging to the same rows as the first memory elements. A potential corresponding to data to be programmed is applied to the first memory element via the even-numbered bit line and a potential which suppresses programming is applied to the second memory element via the cell source line while the odd-numbered bit lines are kept in an electrically floating state when data is programmed into the first memory element.
REFERENCES:
patent: 5923587 (1999-07-01), Choi et al.
patent: 6058042 (2000-05-01), Nobukata et al.
patent: 6353242 (2002-03-01), Watanabe et al.
patent: 6704239 (2004-03-01), Cho et al.
patent: 7245528 (2007-07-01), Shibata et al.
patent: 2002/0117756 (2002-08-01), Yamashita
patent: 2005/0259466 (2005-11-01), Kim
patent: 2007/0133287 (2007-06-01), Hosono
patent: 1 349 214 (2003-10-01), None
patent: 8-195393 (1996-07-01), None
patent: 2000-91546 (2000-03-01), None
Ken Takeuchi, et al., “A Source-line Programming Scheme for Low Voltage Operation NAND Flash Memories”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 37-38, Jun. 1999.
Ken Takeuchi, et al., “A Double-Level Vth Select Gate Array Architecture for Multi-Level NAND Flash Memories”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 69-70, Jun. 1995.
Elms Richard T.
Kabushiki Kaisha Toshiba
Oblon, Spivak, McClelland, Maier, P.C.
Wendler Eric
LandOfFree
NAND flash memory and data programming method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with NAND flash memory and data programming method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and NAND flash memory and data programming method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3921084