Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2007-10-17
2010-02-09
Luu, Pho M (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185260, C365S185330, C365S185270, C365S185240
Reexamination Certificate
active
07660157
ABSTRACT:
A NAND flash memory, including a memory cell array, a row decoder, and a sense amplifier. In a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by the row decoder, a drain-side select gate line and the source-side select gate line are charged to a third voltage, which is higher than the ground potential and is equal to or lower than the second voltage.
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U.S. Appl. No. 12/406,477, filed Mar. 18, 2009, Maejima.
Isobe Katsuaki
Maejima Hiroshi
Bui Tha-O
Kabushiki Kaisha Toshiba
Luu Pho M
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
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