NAND flash memory

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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Details

C365S185170, C365S185240, C365S185260, C365S185270, C365S185330

Reexamination Certificate

active

07916541

ABSTRACT:
A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.

REFERENCES:
patent: 6418058 (2002-07-01), Sakui et al.
patent: 6512703 (2003-01-01), Sakui et al.
patent: 6522583 (2003-02-01), Kanda et al.
patent: 6667904 (2003-12-01), Takeuchi et al.
patent: 7301809 (2007-11-01), Sakui et al.
patent: 2006/0133150 (2006-06-01), Shibata
patent: 2007/0255893 (2007-11-01), Takeuchi
patent: 2008/0094903 (2008-04-01), Maejima et al.
patent: 2001-332093 (2001-11-01), None
patent: 2006-85839 (2006-03-01), None
patent: 2008-47219 (2008-02-01), None

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