Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2004-09-02
2008-11-25
Phan, Trong (Department: 2827)
Static information storage and retrieval
Floating gate
Multiple values
C365S185170, C365S185180, C365S185290, C365S185330
Reexamination Certificate
active
07457156
ABSTRACT:
NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize depletion mode floating gate memory cells. Depletion mode floating gate memory cells allow for increased cell current through lower channel rdsresistance and decreased “narrow width” effect, allowing for increased scaling of NAND memory cell strings. In addition, the required voltages for reading and programming operations are reduced, allowing the use of more efficient, lower voltage charge pumps and a reduction circuit element feature sizes and layouts. Cell inhibit of unselected cells is also increased, reducing the likelihood of cell disturb in the memory array. Operation speed is improved by increasing read current of the selected NAND string and by increasing the ability to overcome the RC time constants of circuit lines and capacitances through lowered voltage swings and increased current supplies.
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Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
Phan Trong
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