Static information storage and retrieval – Floating gate – Particular biasing
Patent
1990-06-04
1991-08-27
Fears, Terrell W.
Static information storage and retrieval
Floating gate
Particular biasing
36518901, G11C 1300
Patent
active
050439421
ABSTRACT:
A NAND cell type EEPROM has a substrate, parallel bit lines formed above the substrate, and a memory cell section including an array of NAND type cell units associated with the same corresponding bit line. Each of the NAND type cell units has a series-circuit of eight data storage transistors and at least one selection transistor. Each data storage transistor has a floating gate for storing carriers injected thereinto by tunneling and a control gate respectively connected to word lines. A control gate driver circuit is provided in common for all the NAND type cell units that are assisted with the same bit line. Transfer gates are connected between the common driver circuit and the NAND cell units.
REFERENCES:
patent: 4233526 (1980-11-01), Kurogi et al.
patent: 4677590 (1987-06-01), Arakawa
patent: 4694314 (1987-09-01), Terada et al.
Itoh Yasuo
Iwata Yoshihisa
Momodomi Masaki
Odaira Hideko
Tanaka Tomoharu
Fears Terrell W.
Kabushiki Kaisha Toshiba
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