NAND based resistive sense memory cell architecture

Details NAND based resistive sense memory cell architecture NAND based resistive sense memory cell architecture

2008-11-12

2010-11-09

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Format or disposition of elements

C365S072000, C365S148000, C365S185050, C365S185170

Reexamination Certificate

active

07830693

ABSTRACT:
Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.

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