NAND architecture memory devices and operation

Details NAND architecture memory devices and operation NAND architecture memory devices and operation

2005-12-20

2009-02-10

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S063000, C365S072000, C365S051000, C365S185050

Reexamination Certificate

active

07489546

ABSTRACT:
Non-volatile memory devices utilizing a modified NAND architecture where both ends of the NAND string of memory cells are selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory cells can be accomplished in the same manner as a traditional NAND memory array. However, reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device.

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