N-wide bypass for data dependencies within register alias table

Details N-wide bypass for data dependencies within register alias table N-wide bypass for data dependencies within register alias table

1993-09-30

1996-08-20

Geckil, Mehmet

Boots, shoes, and leggings

395375, 364DIG1, 3642463, 364238, 364239, G06F 900, G06F 1202

Patent

active

055487769

ABSTRACT:
A bypass mechanism within a register alias table unit (RAT) for handling source-destination data dependencies between operands of a given set of operations issued simultaneously within a superscalar microprocessor. Operations of the given set are presented in program order and data dependencies occur when a source register of particular operation is also utilizes as a destination register of a preceding operation within the given set of operations. At this occurrence, the initial read of the RAT unit will not have supplied the most current rename of the source register. The present invention includes a comparison mechanism to detect this condition. Also included is a bypass mechanism for bypassing the physical source register output by the initial read of the RAT unit with a recently allocated physical destination register assigned to the preceding operation having the matched physical destination register. In general the RAT unit provides register renaming to provide a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs, for instance) to eliminate false data dependencies that reduce overall superscalar processing performance for the microprocessor. The bypass mechanism of the present invention handles both floating point and integer registers and, in addition, a second bypass mechanism is included in the RAT priority write operation.

REFERENCES:
patent: 4574349 (1986-03-01), Rechtschaffen
patent: 4992938 (1991-02-01), Cocke et al.
patent: 5134561 (1992-07-01), Liptay
patent: 5197132 (1993-03-01), Steely, Jr. et al.
patent: 5303358 (1994-04-01), Baum
Val Popescu, et al. entitled, "The Metaflow Architecture," IEEE Micro, Jun. 1991, pp. 10-13, 63-73.
Author, Mike Johnson, entitled Superscalar Microprocessor Design, Advance Micro Devices, Prentice Hall Series in Innovative Technolgoy, 1991, pp. 1-289.

Affiliated with

Also associated with

Rating

N-wide bypass for data dependencies within register alias table does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with N-wide bypass for data dependencies within register alias table, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and N-wide bypass for data dependencies within register alias table will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2338111