N- well CMOS process on a P substrate with double field guard ri

Details N- well CMOS process on a P substrate with double field guard ri N- well CMOS process on a P substrate with double field guard ri

1983-08-31

1986-03-11

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29578, 148 15, 357 42, 357 52, H01L 21265, H01L 2176

Patent

active

045744670

ABSTRACT:
CMOS transistors are fabricated in a P substrate using N- well regions. These wells are positioned to prevent aluminum spiking in the N channel devices. After P guard rings are formed for both P and N channel devices, additional masking and implantation are performed to produce N guard rings in the P channel devices. Before the transistors are formed, an implantation of P type impurities is performed causing the P channel devices, when they are formed, to have a PMOS buried channel.

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