N-well and N + buried layer isolation by auto doping to...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...

Reexamination Certificate

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C257SE27064

Reexamination Certificate

active

07436043

ABSTRACT:
A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common P+buried layer (PBL). The method for forming the substrate usable in a semiconductor device includes forming the NBL in a designated low voltage area of a negatively biased P-type semiconductor substrate, forming the PBL in a section of the NBL area by implanting P-type impurity ions such as indium into the PBL, and growing a P-type epitaxial layer over the PBL using conditions that cause the P-type impurity ions to diffuse into the P-type epitaxial layer such that the PBL extends into the NBL. Low-voltage P-well areas are also formed in the P-type epitaxial layer and contact the PBL.

REFERENCES:
patent: 5156989 (1992-10-01), Williams et al.
patent: 5786617 (1998-07-01), Merrill et al.
patent: 6403992 (2002-06-01), Wei
patent: 6594132 (2003-07-01), Avery
patent: 2003/0122195 (2003-07-01), Tada et al.
patent: 2005/0056907 (2005-03-01), Maeda
Wolf et al., Silicon Processing for the VLSI Era, 2000, Lattice Press, vol. 2 2nd ed., p. 832.

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