N-way circular phase interpolator for generating a signal...

Details N-way circular phase interpolator for generating a signal... N-way circular phase interpolator for generating a signal...

2000-03-23

2001-12-11

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C116S246000, C116S274000

Reexamination Certificate

active

06329859

ABSTRACT:

FIELD OF INVENTION
The present invention relates to generation of clock signals in electronic circuits, and more particularly, to generation of clock signals having externally tunable phase and frequency.
DESCRIPTION OF THE RELATED ART
Many electronic systems, such as communication systems, require clock signals whose phase and frequency can be tuned externally. One such system is the Clock and Data Recovery (CDR) circuit. A CDR circuit recovers the embedded clock from a baseband non-return-to-zero (NRZ) or return-to-zero (RZ) data stream and generates a clean data stream (e.g., data that does not have timing jitter due to e.g. the limited bandwidth of the transmission channel). The clock recovery function of a CDR is typically performed with a Phase-Locked Loop (PLL) which requires a tunable clock signal, such as that generated by a Voltage-Controlled Oscillator (VCO).
However, VCOs are generally susceptible to noise, supply voltage, process parameter and temperature variations. Therefore, VCOs and PLLs incorporating VCOs exhibit undesirable characteristics when they are used, for example, in mixed-signal Integrated Circuits (ICs).
One well known class of circuits that reduces the above problems is the Delay-Locked Loop (DLLs). A DLL generates a clock signal that has the same frequency as that of a reference clock signal but whose phase may deviate from that of the reference clock by an amount that is within a pre-defined range.
However, many systems require plesiochronous clocks, i.e. clocks whose frequencies vary within a small range centered around a nominal value. For example, the 1000Base-X versions of the Gigabit Ethernet standard require a bit-rate deviation of less than 100 parts per million from the nominal bit rate of 1.25 Giga-bit per second. Such plesiochronous clocks cannot be generated by using DLLs.
One known method for generating a tunable plesiochronous clock signal is “phase picking”. According to this technique, a number of evenly spaced phases of a reference clock signal are first generated (e.g., 16 as shown in FIG.
1
). The multiple phases required for this technique could be obtained, for example, by tapping a multi-stage ring oscillator (see
IEEE Journal of Solid State Circuits,
Vol. 25, No. 6, December 1990 “30-
Mhz Hybrid Analog/Digital Clock Recovery Circuit in
2-&mgr;
m CMOS
by Beomsup Kim, David N. Helma, and Paul R. Gray”; and
IEEE Journal of Solid State Circuits,
Vol. 31, No. 12, December 1996
“A
0.8
&mgr;m CMOS
2.5
Gb/s oversampling Receiver and Transmitter for Serial Lines
” by Chih-Kong Ken Yang and Mark A. Horowitz”). Subsequently, the tuned clock signal is generated by dynamically tapping a particular phase.
In the phase picking technique, the frequency of the generated clock signal may be different from that of the reference clock signal. If the selected tap moves counter-clockwise, the frequency of the generated clock signal increases over that of the reference clock. If, on the other hand, the selected tap moves clockwise, the frequency of the generated clock signal becomes lower than that of the reference clock.
Often, the phase selection occurs at a lower rate than the frequency of the reference clock. Furthermore, it takes many updates to achieve an excess phase (i.e., the difference between the phase of the generated clock and that of the reference clock) of 2&pgr;. Consequently, the excess frequency (i.e., the difference between the frequency of the generated clock and that of the reference clock) generated as a result of the movement of the tapped phase is usually small compared to the reference clock frequency, making the phase-picking technique suitable for use in a plesiochronous environment. However, because it is difficult to obtain and distribute many phases of a clock signal, the phase picking technique does not lend itself to fine tuning of phase control.
One well known technique for overcoming the above-mentioned problems associated with the phase picking is the Circular Phase Interpolation (CPI) (see ISSCC Dig. Tech. Papers, pp. 160-161, February 1993,
“PLL design for a
500
MB/s Interface
” by M. Horowitz, et al.).
FIG. 2
illustrates the four phases, namely I, Q, {overscore (I)} and {overscore (Q)}, which the CPI uses to generate a signal which has the desired phase. As seen from
FIG. 2
, the four shown phases are 90° apart. According to the CPI technique, the phase of any vector is a weighted sum of two of the above four phases. For example, the phase of vector X is a weighted sum of phases I and Q. Similarly, the phase of vector Y is a weighted sum of phases Q and {overscore (I)}. Consequently, by selecting the proper weights, a signal whose phase is a weighted sum of the above phases is obtained.
FIG. 3
shows a known Linear Phase Interpolator (LPI)
10
for linearly interpolating signals A and B, which are respectively represented by a pair of differential signals A
+
, A
−
and B
+
, B
−
. In
FIG. 3
, output signal OUT is represented by differential signals OUT
+
and OUT
−
. As seen from
FIG. 3
, LPI
10
applies weight signals I
A
and I
B
respectively to signals A and B to generate signal OUT. Phases &thgr;
A
, &thgr;
B
and &thgr;
OUT
, which are respectively represented by signals A, B, and OUT, are approximately linearly related, as shown below in equation (1):
θ
OUT
=
θ
fix
+
θ
A
×
I
A
Io
+
θ
B
×
I
B
I
O
(
1
)
where I
o
=I
A
+I
B
.
FIG. 4
shows a four phase CPI circuit
100
. CPI
100
includes LPI
10
(also shown in FIG.
3
), multiplexer (MUX)
20
, Digital-to-analog (D-to-A) converters
30
,
40
, and combinational logic
50
. Combinational logic
50
receives a digital control word consisting of 2+m bits. The two most significant bits (MSB) of the control word select from among the four phase signals I, Q, {overscore (I)}, {overscore (Q)}. The remaining m bits of the control word are applied to D-to-A converters
30
and
40
which convert the m bits into analog currents I
A
and I
B
, representing the weights applied to the selected phases. Accordingly, the least significant bit (LSB) (i.e., the smallest phase step) corresponds to a phase 2&pgr;/2
2+m
. MUX
20
receives the MSBs to select and thereby supply to LPI
10
the two signals A and B used for generating signal OUT. Note that a 2&pgr; phase, in radian units, is equivalent to a 360° phase, in degree units.
CPI
100
of
FIG. 4
typically operates under the “unitary update” rule, which requires that each new digital control word differ from the previous one by either 0 or ±1 LSB in order to prevent glitches at the generated phase. In CPI
100
, when the generated phase moves from point X to point Y (see FIG.
2
), the generated phase must cross phase Q. To provide the proper phase, input phase, signal I is blocked from reaching the output terminal of MUX
20
; instead, input phase signal I is delivered to the output terminal of MUX
20
. Consequently, unless the weight applied to phase signal I is zero at the time of the input transition, a glitch appears at the generated signal OUT. To prevent the glitch from appearing, the unitary update rule must be met.
In order to reduce quantization error, which causes jitter in the phase, and to increase precision, smaller one-LSB steps are required. To achieve smaller steps, either one of the following techniques may be used: 1) increase the number of phase signals (i.e., phase signals I, {overscore (I)}, etc., which constitute the coarse phases); 2) add more bits to the interpolative control signal (i.e., add more bits to the m-bit interpolative control signal FINE of FIG.
4
). However, both of the above techniques increase system complexity and power consumption. In addition, adding more bits for interpolative control places more stringent linearity requirements on the D-to-A converters
30
,
40
and linear phase interpolator
10
. Moreover, as more bits are added to the control word to increase precision, because of the unitary update rule, a 2&pgr; phase rotation takes longer to c

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